ADI Linear Regulator LT3073 - How to Realize Multi-Device Parallel Connection?

Semiconductor Integrated Circuits (ICs)
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The core goal of paralleling multiple LT3073 units is to enhance the output current capability while optimizing noise performance and thermal distribution.

  • The output current is approximately proportional to the number of parallel units (N). For example:

    • 2 parallel units: Maximum output current up to 6A;
    • N parallel units: Theoretical maximum output current ≈ 3A × N (current loss of ballast resistors should be considered, so the actual value is slightly lower). This meets the high-current load requirements of FPGAs, high-power RF modules, etc.

  • The output noise decreases in the ratio of √N (N is the number of parallel units). For example:

    • Single unit noise: 1.2μVrms (10Hz~100kHz, CREF=4.7μF);
    • 2 parallel units: Noise ≈ 1.2μVrms / √2 ≈ 0.85μVrms;
    • 4 parallel units: Noise ≈ 1.2μVrms / 2 = 0.6μVrms. This makes it more suitable for noise-sensitive applications (such as RF power supplies, high-precision data converters).

1. Parallel Connection Method and Principle

Paralleling multiple LT3073 units must strictly follow pin connection rules, current sharing design, and PCB layout requirements. The core principle is to realize the coordinated operation of multiple devices through pin synchronization + current sharing via ballast resistors.

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Multi-LT3073 Parallel Connection (Image source: ADI)

The specific steps are as follows:

1.1 Forced Synchronous Connection of Key Pins

To ensure consistency in output voltage, reference voltage, and control logic across multiple devices, the following pins must be directly shorted:

  • IN Pins: The IN pins of all LT3073 units are connected to the same input power supply to ensure consistent input voltage and avoid uneven output current caused by input voltage differences.
  • OUT Pins: The OUT pins of all LT3073 units are connected to the same common load terminal as the total output terminal; the exposed pad must be soldered to a large-area copper layer on the PCB to improve heat dissipation efficiency.
  • REF Pins: The REF pins of all LT3073 units are shorted to form a “multi-reference voltage source average value”, which offsets the reference voltage deviation of a single device and ensures output voltage consistency.
  • EN Pins: The EN pins of all units are connected to the same enable signal to ensure synchronous turn-on/off of multiple devices and avoid current imbalance caused by some devices operating in advance.
  • BIAS/BIASF Pins: Each LT3073’s BIASF pin must be connected in parallel with a separate 2.2μF bypass capacitor (to meet stability requirements), and all BIAS pins are connected to the same BIAS power supply.

1.2 Key Design of Ballast Resistors

To solve the current sharing problem caused by differences in output impedance among multiple devices, a ballast resistor must be connected in series between the OUT pin of each LT3073 and the common load. The core requirements are as follows:

  • Resistance Selection: The typical value is 2mΩ, which can be realized through PCB traces (e.g., for 2oz copper thickness and 20mil wide PCB traces, the resistance per inch is approximately 13.6mΩ; the length must be precisely controlled to ensure the resistance value); dedicated current-sensing resistors can also be used.
  • Installation Position: The ballast resistor must be placed between the “OUT pin of the LT3073” and the “feedback SENSE tap” (i.e., the SENSE pin must be connected to the end of the ballast resistor close to the load). This ensures that the feedback loop can compensate for the voltage drop across the ballast resistor without affecting the output voltage accuracy.
  • Process Requirements: Soldering is prohibited in the ballast trace area to prevent solder from changing the trace resistance and causing current sharing failure.

1.3 Special Handling of VIOC Pins (If Used)

If the upstream switching converter needs to be controlled via VIOC (to optimize input-output dropout voltage and reduce power consumption), only one of the LT3073s’ VIOC pins needs to be connected to the FB pin of the switching converter, and the VIOC pins of the other LT3073 units can be left floating.

1.4 Auxiliary PCB Layout Requirements

  • Heat Dissipation Design: The IN/OUT pins must be soldered to large-area copper layers and connected to inner-layer copper layers via thermal vias to distribute the power consumption of each device (the total power consumption remains unchanged after paralleling, but the power consumption of a single device is reduced, resulting in a lower junction temperature).
  • Impedance Control: The IN/OUT traces must be short and wide to reduce parasitic inductance and avoid voltage drop under high current; each device’s input side must be connected in parallel with a 47μF input capacitor to suppress input transient noise.

Summary

The core of paralleling multiple LT3073 units lies in pin synchronization + current sharing via ballast resistors. By shorting the IN/OUT/REF/EN pins to ensure voltage and control consistency, and using 2mΩ ballast resistors to achieve current sharing, the final goal of higher output current, lower noise, and better thermal distribution is realized. This solution is suitable for high-current, low-noise, and high-reliability power supply scenarios (such as FPGA core power supplies, RF power amplifier power supplies, etc.).

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