Please refer to out previous article Part 5 of the additional setup for the DE-25 Agilex 5 Simics Simulator before preceeding with the next steps. The goal of this article is to complete the build process of a Zephyr RTOS application that will run in the Agilex™ 5 Simics Virtual Platform relevant to the DE-25 FPGA Dev Kit
In our previous article Part 5 we almost completed the build process for the the Zephyr RTOS DigiKey drinking coffee cup philosophers in the Agilex 5 Simics Simulator. To complete this process proceed with the next step to create bl2.hex from bl2.bin as follows,
cd $TOP_FOLDER/qspi_bin
aarch64-none-linux-gnu-objcopy -v -I binary -O ihex --change-addresses 0x00000000 bl2.bin bl2.hex
Now we are ready to create flash_image_jic.rpd qspi image from fip.bin and bl2.hex,
cd $TOP_FOLDER/qspi_bin
ln -s $TOP_FOLDER/ghrd_a5ed065bb32ae6sr0_hps.sof agilex5_factory.sof
quartus_pfg -c qspi_flash_image_agilex5_boot.pfg
Now create a Simics project directory under the top directory,
cd $TOP_FOLDER
rm -rf project-1
mkdir project-1
cd project-1
Under the new project directory just defined, enable the agilex5e-universal virtual platform as shown next,
simics_intelfpga_cli --deploy agilex5e-universal
Build the virtual platform elements as follows,
make
To boot from the QSPI binaries,
cd $TOP_FOLDER/project-1
cputypestring=""
if [ $cputype = "a76" ]; then
cputypestring='$hps_boot_core = 2
$hps_core0_1_power_on = TRUE
$hps_core2_power_on = TRUE
$hps_core3_power_on = TRUE '
fi;
tee zephyr_qspi.simics << 'EOF'
# TOP-LEVEL CONFIG Script TO BOOT ZEPHYR.
local $board_name = "system.board.fpga"
# Ensure the nand_mem.img & bl2.bin paths are relative to the simics executable
# First stage boot loader, ATF BL2 path
$fsbl_image_filename = ../qspi_bin/bl2.bin
#Boot from QSPI
$qspi_image_filename = ../qspi_bin/flash_image_jic.rpd
# Enable Console
$create_hps_serial0_console=TRUE
EOF
echo "$cputypestring" >> zephyr_qspi.simics
echo 'run-command-file "targets/agilex5e-universal/agilex5e-universal.simics"
run' >> zephyr_qspi.simics
At this point we are ready to run the Zephyr RTOS application demo,
cd $TOP_FOLDER/project-1
ln -s zephyr_qspi.simics zephyr.simics
./simics zephyr.simics
...
...
....
HPS Status:
Status of system.board.fpga.soc_inst.hps_subsys.agilex_hps [class vp_intel_agilex_5_soc]
========================================================================================
Setup:
Top component : system
Instantiated : True
Attributes:
boot_core : 0
combophy_iface_select_enable : False
core0_1_power_on : True
core2_power_on : True
core3_power_on : True
create_hps_serial0_console : True
create_hps_serial1_console : False
fsbl_image : ../qspi_bin/bl2.bin
hps_cpu_freq_mhz : 400
reset_vector : 0
stepping : A0
Connections:
f2s_fpga_irq[0] : system.board.fpga.soc_inst.periph_subsys:periph_button_irq
hps2fpga_0_down : system.board.fpga.soc_inst.example_design:design_mem_conn
hps_conn : system.board.fpga.soc_inst.hps_subsys.emif:emif_conn
lwhps2fpga_down : system.board.fpga.soc_inst.periph_subsys:periph_mem_conn
serial0 : system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0:serial
usb31_slot : system.board.fpga.soc_inst.hps_subsys.agilex_hps.usb31:usb31_hps_slot
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.gicr[0] info] Calling hard reset default
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.gicr[0] info] pendr clear
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.gicr[1] info] Calling hard reset default
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.gicr[1] info] pendr clear
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.gicr[2] info] Calling hard reset default
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.gicr[2] info] pendr clear
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.gicr[3] info] Calling hard reset default
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.gicr[3] info] pendr clear
[system.board.fpga.soc_inst.hps_subsys.agilex_hps.uart0.bank.regs unimpl] Write to unimplemented field regs.FCR.DMAM (value written = 0x1, contents = 0).
This will launch the Agilex™ 5 Simics Virtual Platform relevant to the DE-25 FPGA Dev Kitr using the zephyr.simics in a separate window as shown in the next video of this demo,
This Dining philosophers Agilex™ 5 Simics Virtual Platform demo modified for Coffee Drinking can be configured to use different object types for its synchronization: SEMAPHORES, MUTEXES, STACKS, FIFOS and LIFOS.
The DE-25 FPGA Dev Kit is a powerful platform featuring an HPS/FPGA Agilex 5 (available as D-Series and E-Series depending on the case) capable of implementing Tensor AI slices,
that go beyond what traditional/classical old school DSP slices implemented in the past,
and it is available at DigiKey.
Have a wonderful day!