Hi @maalikKyzer! I got in touch with the board house. They provided another updated document that shows the Df and Dr values. I’m going to edit my previous posts to show this file, but here it is:
DKRed - 4 layer Stackup v2.pdf (392.8 KB)
As for your second question, the boardhouse said, “Tg is an attribute which 370HR meets.”
Thank you again for your questions on these. I apologize for all the revisions but want to get this right with all the information needed.
No worries @Linzee_1029 . Thanks for the update.
One final question. Board houses tend to provide impedance trace recommendations.
Using Altium, when using the 4 layer PCB stackup info, I calculated two impedance profiles for
as shown in the attached picture.
Assume the reference GND plane is the 2nd layer and these trace parameters are for the Top layer only.
Can I verify my width and clearance values with your board house?
If the board house has a better number, I’d like to use that.
Hi, I was wondering if you plan on manufacturing stencils along with the PCB in the near future. Would love to try the service but ordering a separate stencil from another company adds delays and sometimes complication. Is it something you are working on or do you plan on producing only PCBs?
Stencils are definitely on the roadmap. 
