This engineering brief describes how to construct a state machine using the Siemens LOGO! PLC. The technique is reminiscent of a rudimentary state machine constructed using discrete 74-series digital logic. Considerable attention is directed toward orderly layout in the LOGO!'s function block language.
The technique is demonstrated using a Siemens LOGO! 9 PLC and a Honeywell SPS-R360D-NBMS0101 as shown in Figure 1. In this application, the Honeywell sensor is used to mimic the dial on a combination safe. Note that the DigiKey technicians have added several pieces to the sensor for presentation.
Download the LOGO! 9 project here:
Initial.wnp (188.8 KB)
The password is “password”.
Key Takeaways
- The state bits are maintained using the LOGO!-native latch relay (set/reset) block.
- A one-hot technique is used where one, and only one, bit is active at any given time.
- The technique is practical for small machines with up to five discrete states. Larger state machines are possible but become increasingly complex even with rigorous attention to program layout.
- A function block diagram is used to stay within the default LOGO! software configuration.
- The LOGO! logic symbols are function calls, not physical logic gates. The code is executed sequentially, not everything all at once like an FPGA. This must be considered to prevent glitched outputs in the state machine.
This article is part of the DigiKey Field Guide for Industrial Automation
Location: Program It → PLC → Siemens LOGO!
Difficulty: 
Engineer — difficulty levels explained
Author: Aaron Dahlen | MSEE | Senior Applications Engineer, DigiKey
Last update: 10 Jun 2026
Figure 1: The Honeywell rotary sensor is shown on the author’s workbench alongside a LOGO! 9 PLC.
Honeywell Sensor as Safe Dial
The state machine is designed to mimic a combination dial on a safe. The state will advance as the user rotates the dial according to the hard-coded combination 14, 75, and 29.
The sensor provides a 4-20 mA signal while the LOGO! accepts a 0-10 VDC analog input. The input voltage is developed across a 470 Ω resistor. The sensor full scale values are scaled to 0-100 using a LOGO! analog amplifier. Finally, analog threshold triggers are used to detect specific numbers that are contained within the dial combination. For example, memory location M52 is used to detect the number 75.
What state-machine building blocks are available?
The latching relay is a LOGO! building block for state machines. In the physical world, the latching relay is commonly implemented with two coils. It will physically hold the state based on which coil was activated. The IDEC RY2KS-UDC24V, as shown in Figure 2, is a representative dual coil latching relay. We can see the two coils as well as the physical mechanism that holds the relay armature in its discrete position.
Memory is the most important aspect of the latching relay. It contains a binary memory location that retains the state based on the last activated input. For the LOGO!, the latching relay provides two states.
- Activating Set will set the Q output.
- Activating Reset will clear the Q output.
- The reset input has priority over the set line.
Figure 2: Image of a dual coil latching relay.
State Machine for the Siemens LOGO!: One-Hot Logic Using Latching Relays
Figure 3 presents a five-state, one-hot state machine. One of my former students remarked that the structure looks similar to a state machine built using 74-series logic.
- The state is held in the latching relays (designated RS).
- AND gates (&) are used to set the individual latches.
- OR gates (≥ 1) are used to clear the individual latches.
- The zero state is shown at the top of the diagram. It is asserted when none of the latching relays are set.
Conditions for Resetting a State Bit
Each latch is reset via an OR gate. The top input to each OR gate is a master reset originating from input I1. Each OR gate also receives a signal from the state that sequentially follows it. For example, in Figure 3, the red debug signal is associated with State 2. Observe that this signal is sent to the State 1 latch (B014) via the OR gate (B015). Consequently, advancing to a new state will clear the old state, thereby preserving the one-hot nature of the state machine.
Conditions for Setting the Next State Bit
Each latch is set by an AND gate that combines the current state and the transition condition. The B25 AND block is an example. The LOGO! is currently in State 2. The state transition is waiting for signal M52.
Figure 3: Glitchy implementation of a five-state machine.
Glitch Hazard
CAUTION: This is not a clean implementation. Due to the top-to-bottom left-to-right execution of the code, there is a one-cycle glitch where two state bits are active at the same time. This was verified by ANDing State 2 and State 3 and feeding the result to a latch. This latch is triggered every State 2 to State 3 transition thereby revealing the two-hot glitch.
As an example, consider the Figure 3 debug window which is currently in state 2. Observe that the system will set the State 3 bit when signal M52 is asserted. However, and this is the critical part, the calculations for State 2 have already been completed. Consequently, the one-hot rule is violated and we leave this cycle with both State 2 and State 3 asserted.
Tech Tip: The LOGO! function block logic symbols are function calls, not real-world gates. This is the same hazard as ladder logic when we forget that the coils and contacts are really C-like function calls.
Never forget that you are looking at an abstraction. Under the hood we are dealing with a microcontroller calling prebuilt functions for memory-to-memory operations. This article provides a code example bridging the concepts of microcontroller and PLC programming.
Glitch-Free State Machine
Bottom line: Prevent the two-state glitch by delaying the state transition by one scan cycle.
The source of the hazard is the natural result of logic (code) consecutively executed from top-to-bottom and left-to-right. In our example, we cannot back up to clear State 2 because that portion of code has already been called. Instead, a reasonable solution is to inhibit State 3 while State 2 is active, thereby maintaining the one-hot pattern.
One simple solution is shown in Figure 4. For clarity, Figure 4 keeps the Figure 3 state machine intact. The only addition is the AND gate to prevent two states from simultaneously activating. Effectively, we have delayed the state transition by one scan cycle.
Figure 4: Glitch-free state machine.
Smart Use of Memory Locations
Resist the temptation to use the default software-provided memory locations. Instead, deliberately use the memory names to your advantage. For example, the lower left of Figure 3, there are five flags (M blocks). Observe that the top block has been assigned binary memory location M100. The remainder are sequentially numbered, ending at M104. Together, they represent the one-hot states of the machine as described in the Tech Tip.
Note that the memory assignments are not strictly required as they duplicate the values held in the latching relays. However, they form a clean left-hand matrix of wires from which the remainder of the state machine is tapped.
Tech Tip: There are multiple ways to represent state. Both integer representation and one-hot are commonly used in industrial control systems. Integer representation requires an integer-type state variable, a series of numeric comparators, and move operators. On the other hand, the one-hot technique stores each state in a discrete memory location.
The one-hot representation is a straightforward process in the LOGO! using latching relays. A side benefit is that a clean one-hot signal is present for each state. This greatly simplifies the next-state and output logic. For example, a dedicated HMI output can be built for each state.
There is a design tradeoff as the graphical structure for the one-hot machine becomes unwieldy. This is why I recommend limiting the size to about five states as shown in Figure 3.
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About this Author
Aaron Dahlen, LCDR USCG (Ret.), is a Senior Applications Engineer at DigiKey in Thief River Falls. His background in electronics and industrial automation was shaped by a 27-year military career as both technician and engineer, followed by over a decade of teaching.
Dahlen holds an MSEE from Minnesota State University, Mankato. He has taught in an ABET-accredited electrical engineering program, served as coordinator of an electronic engineering technology program, and instructed military technicians in component-level repair.
Today, he has returned to his home in northern Minnesota, completing a decades-long journey that began with a search for capacitors. Read his story here.