Q1 - I’m getting a “no acknowledge” (NACK) when I try to communicate with the power monitor?
TI Answer;
When a TI power monitor, for example the INA238, fails to acknowledge (NACK) I2C communications, the issue typically stems from a violation of the physical layer requirements (i.e. voltage thresholds, impedance matching) or timing constraints.
- Logic Level Non-Compliance (VIL/VOL Conflict)
The most frequent cause of a NACK is the failure of the master (MCU) to pull the SDA/SCL lines below the INA238’s Input Low Voltage (VIL) threshold.
- The Threshold Gap: The INA238 requires a logic low to be less than 0.4V, but it should be noted that some of our digital devices require logic level to be less than 0.4V or less than 0.3*Vs, so please refer to the device’s datasheet to find out the VIL logic level. We recommend the logic level should be at least 100-200mV below the VIL spec found in the datasheet for extra padding.
- The Voltage Offset Issue: When using certain I2C buffers or digital isolators (like the ISO154x series), the “Side 1” output often employs a diode-blocked voltage offset resulting in a VOL of ~0.6V to 0.8V. If the ground potential between the MCU and the INA238 shifts slightly, or if the pull-up resistors are too strong, the “low” signal may hover near 1.0V. If the INA238 does not register a clean transition below VIL, it will not recognize the start condition or the address bits, resulting in a NACK.
With reference to the ISO154x series, “Side 2” may have a sufficiently low logic output within the INA’s threshold, depending on the supply voltage to “Side 2”.
- Impedance and Pull-Up Resistor Optimization
I2C is an open-drain architecture; the rise time ( tr) is governed by the RC constant of the bus.
- Over-damping: If pull-up resistors are too high (e.g., >10kΩ), bus capacitance prevents the signal from reaching the VIH (Input High) threshold before the next clock pulse. This rounds the square wave, leading to sampled bit errors.
- Under-damping: Conversely, if it is too low (e.g., <1kΩ), the INA238 or MCU may lack the sink current capability (typically 3mA) to pull the line down to a valid VIL, causing the controller to see a constant “high” state.
- Timing and Signal Integrity
The INA238 supports Fast-mode (400kHz) and High-speed mode. However, signal reflections or excessive bus length can cause ringing or undershoot on timing plots. If the SDA line transitions are too slow relative to the SCL rising edge (violating setup time), or if there is noise on the clock line that the INA238 interprets as a double-pulse, the device’s internal state machine will desynchronize and fail to issue an ACK.
In addition, when connecting the SDA pin to either A0 or A1 to set the device address, additional hold time (tHDDAT) of 100 ns is needed on the MSB of the I2C address to verify the correct device addressing.
The Recommended Solution for Logic Level Conflict:
Logic Level Translators
When the MCU and INA238 operate on different voltage domains or when VIL thresholds are marginal, the most robust solution is the integration of an Active Logic Level Translator (e.g., TI PCA9306 or TCA9517).
Why this solves the NACK:
- Voltage Isolation: A translator decouples the capacitive loading of two different bus segments, allowing the INA238 to “see” a signal referenced perfectly to its own local supply.
- Current Boosting: Devices like the TCA9517 provide active “low” drive, ensuring that even with significant bus capacitance, the VOL is driven closer to 0V, well below the VIL threshold of the INA238.
- Bidirectional Precision: It ensures that the ACK bit sent by the INA238 is correctly translated back to the MCU’s specific logic levels, preventing “ghosting” where the slave responds but the master fails to read it.
After reviewing the information above, a lot more can be found on the Original TI Support Forum