Question about PI2MEQX2505Q for MIPI CSI-2 4-lane unidirectional use

Semiconductor Integrated Circuits (ICs)
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1

Hello,

We are considering using PI2MEQX2505Q as a MIPI D-PHY ReDriver for a MIPI CSI-2 application.

We have already contacted Diodes Incorporated directly regarding this question, but we have not received a reply yet. Therefore, we would appreciate it if DigiKey could help confirm this point with Diodes or provide any available technical guidance.

Target application:

  • Interface: MIPI CSI-2

  • Lane configuration: 1 clock lane + 4 data lanes

  • Data rate: 1.04 Gbps per data lane

  • Direction: Source to sink only

  • DSI bidirectional LP mode: Not required

  • Sink side condition: The receiver input is always terminated with 50 ohms, and the termination cannot be disabled during LP mode

We would like to confirm the following points:

  1. Can PI2MEQX2505Q be used for a unidirectional MIPI CSI-2 application using all four data lanes?

  2. Does Data Lane0 have any special behavior or design constraint related to DSI bidirectional LP mode?

  3. Can the device operate correctly if the CSI-2 sink side is always 50 ohm terminated, including during LP mode?

  4. Is there any requirement that Data Lane0, or any other lane, must be connected to an unterminated LP receiver during LP mode?

  5. If PI2MEQX2505Q is not suitable for this condition, could you recommend an alternative device for a 1-clock + 4-data-lane MIPI CSI-2 unidirectional ReDriver application?

We would appreciate it if DigiKey or Diodes could confirm this point, because our application cannot disable the 50 ohm termination on the sink side.

Thank you.

2

Hello shinichi.mikami, welcome to the TechForum! Thank you for the detailed question. I am currently asking my colleagues as I’m not sure how to answer these in-depth questions about the product. Unfortunately, I do not have much experience with MIPI or drivers like this. I may reach out to the manufacturer for technical advice.

3

I’d personally wait for a response from Engineers at Pericom/Diodes… With all these faster high-speed links, we are moving into an era where everything needs a ReDriver/ReTimer to keep signals clean on board. Not everything configurable on this part is available on the ‘base’ datasheet.

Regards,

4

Hello Kaleb and Robert,

Thank you for your replies and for checking with your colleagues or the manufacturer.

I would like to add one correction and clarification to my original question.

In my first post, I wrote that the sink side is always terminated with 50 ohms and that the termination cannot be disabled during LP mode. However, after checking the receiver specification again, I found that the receiver termination is actually a 100-ohm differential termination, and in Dynamic termination mode, the HS termination can be disabled during LP mode.

So the updated sink-side condition is as follows:

  • The sink device is a MIPI D-PHY receiver.

  • In HS mode, the 100-ohm differential termination is enabled.

  • In LP mode, the 100-ohm differential termination is disabled in Dynamic termination mode.

  • The termination switching is controlled by LP/HS detection on the sink receiver side.

With this updated condition, could you please confirm with Diodes whether PI2MEQX2505Q can be used for a unidirectional MIPI CSI-2 application with 1 clock lane + 4 data lanes?

In particular, I would like to confirm whether Data Lane0 has any special requirement due to DSI LP Backchannel support, even when the sink side is a MIPI D-PHY receiver using Dynamic termination and disables the HS termination during LP mode.

Thank you again for your support.