# Taking advantage of FPGA Hardware Development in C with Microchip

**URL:** <https://forum.digikey.com/t/taking-advantage-of-fpga-hardware-development-in-c-with-microchip/26671>\
**Category:** Integrated Circuits (ICs)\
**Tags:** microchip-technology, embedded\
**Created:** [November 11, 2022, 2:13pm UTC](https://forum.digikey.com/t/taking-advantage-of-fpga-hardware-development-in-c-with-microchip/26671 "2022-11-11T14:13:54Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![Rolf\_Horn](https://sea2.discourse-cdn.com/digikey/user_avatar/forum.digikey.com/rolf_horn/32/52867_2.png) [@Rolf\_Horn](https://forum.digikey.com/u/Rolf_Horn)\
**Post date:** [November 11, 2022, 2:13pm UTC](https://forum.digikey.com/t/taking-advantage-of-fpga-hardware-development-in-c-with-microchip/26671/1 "2022-11-11T14:13:54Z")

</div>

**Taking advantage of FPGA Hardware Development in C with Microchip**

With the introduction of [PolarFire™](https://www.digikey.de/de/products/result?s=N4IgjCBcoLQCxVAYygMwIYBsDOBTANCAG4B2aWehA9lANogCsAHGE0yALqEAOALlCBABfEUA) [System-on-Chip (SoC)](https://www.digikey.de/de/products/filter/embedded/system-auf-chip-soc/777), designers now have the ability to design and evaluate the true trade-off of realizing an application using processors or accelerating functions within FPGA fabric. Using the extensions to our development tool chain, this presentation will show how C code can be written for RiscV, evaluated and accelerated by converting it to FPGA logic using SmartHLS.

Presented by **Peter Trott** , Ex-Microsemi

**SmartHLS – Smart High-Level Synthesis supports Better Productivity and Fewer Bugs**

**Productivity: 2-5 X faster design cycle**

**Quality: Fewer bugs, easier to understand & maintain C/C++ code**

**Faster: Accelerated software model verification**

**Ease of Use: FPGA Portability**

**Performance: 2-10 X embedded software acceleration**

**Support for PolarFire®, PolarFireSoC®, SmartFusion®2, IGLOO®2**

 ![image](https://global.discourse-cdn.com/digikey/original/3X/3/6/36a5ac674344a2dadef2463381c4211f23cb5808.png)

![image](https://global.discourse-cdn.com/digikey/original/3X/c/d/cdd062ab28fff12032eac863aed636282a3cb16d.png)

![image](https://global.discourse-cdn.com/digikey/original/3X/2/1/2165f565b7e5e8bd178ea6d6837d66257c50b918.png)

| **Design** | **RTL (Lines)** | **C++ (Lines)** | **Improvement** |
| --- | --- | --- | --- |
| Alpha Blend | 283 | 39 | **7 X** |
| Color Space Conversion (RGB2YCbCr) | 158 | 32 | **5 X** |
| Color Space Conversion (YCbCr2RGB) | 182 | 36 | **5 X** |
| Gaussian Filter | 276 | 65 | **4 X** |
| Digit Recognition | 1,984 | 334 | **6 X** |

**Faster Verification in C++ with**  **significantly fewer lines of code provide accelerated verification, easier to understand and fewer potential bugs!**

**Gaussian Filter in C++ _vs Gaussian Filter handwritten in Verilog  
(65 lines) vs (276 lines without submodules)_**

![image](https://global.discourse-cdn.com/digikey/original/3X/8/7/878429fa4902a52eac783a0beb12316919e98700.png) ![image](https://global.discourse-cdn.com/digikey/original/3X/e/9/e930c4fd560842d3b759e7b17ef3393ba14b0bd4.jpeg)

**More Detailed Information**

**Examples**

[Image Processing on PolarFire Kit](https://github.com/MicrochipTech/fpga-hls-examples/blob/main/Training1/SmartHLS_Training_Session_1.pdf)

[Multi-threaded digit recognition on PolarFire Video Kit](https://github.com/MicrochipTech/fpga-hls-examples/blob/main/Training2/SmartHLS_Training_Session_2.pdf)

[AXI interfaces to DDR and Mi-V soft Processor on Video Kit](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-design-resources/smarthls-compiler)

**Product Documentation**

[SmartHLS Software User Guide](https://microchiptech.github.io/fpga-hls-docs/userguide.html)

[SmartHLS Software Installation Guide](https://microchiptech.github.io/fpga-hls-docs/gettingstarted.html)

[SmartHLS Tutorial](https://www.microsemi.com/document-portal/doc_download/1245532-legup-hls-tutorial)

**Whitepapers**

[Benefits of SmartHLS Whitepaper](https://coredocs.s3.amazonaws.com/smarthls/2021.2/SmartHLS_Benefits_Whitepaper.pdf)

[Migrating Motor Controller C++ Software to a PolarFire® FPGA with SmartHLS](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-design-resources/smarthls-compiler)[Whitepaper](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-design-resources/smarthls-compiler)

**Tutorials and HLS Examples**

[https://github.com/MicrochipTech/[fpga-hls-examples](https://github.com/MicrochipTech/fpga-hls-examples)](https://github.com/MicrochipTech/%5Bfpga-hls-examples%5D(https://github.com/MicrochipTech/fpga-hls-examples))

 ![image](https://global.discourse-cdn.com/digikey/original/3X/4/f/4fa947496c24f946574cb230391d085ba847ce63.png)

[SmartHLS Product Page](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-design-resources/smarthls-compiler)