# ZYNQ Board external clock direct to FPGA

**URL:** <https://forum.digikey.com/t/zynq-board-external-clock-direct-to-fpga/46288>\
**Category:** Development Boards, Kits, Programmers\
**Tags:** evaluation-boards, amd\
**Created:** [November 7, 2024, 3:43pm UTC](https://forum.digikey.com/t/zynq-board-external-clock-direct-to-fpga/46288 "2024-11-07T15:43:05Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![APDahlen](https://sea2.discourse-cdn.com/digikey/user_avatar/forum.digikey.com/apdahlen/32/40191_2.png) [@APDahlen](https://forum.digikey.com/u/APDahlen)\
**Post date:** [November 7, 2024, 4:26pm UTC](https://forum.digikey.com/t/zynq-board-external-clock-direct-to-fpga/46288/3 "2024-11-07T16:26:15Z")

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Welcome back @markatmerlintps,

Understood, you have a PNT application that requires a rock-solid PPS (likely GPS derived).

Thoughts:

1. What is the logic level of your PPS? As memory serves, the ZYNQ has 3.3. VDC logic. You may or may not need a level shifter. Be sure to carefully review the data sheet for PPS and the ZYNQ board.

2. Recommend use of a [synchronizer](https://forum.digikey.com/t/implementing-a-clock-boundary-synchronizer-in-verilog/35809). This will delay you PPS, but by a known ammount.

3. Depending on you timing requirements, the PPS may not be good enough as you will have jitter equal to the clock period of the FPGA. Please consider [this article](https://forum.digikey.com/t/how-to-implement-a-pnt-derived-pulse-per-second-pps-external-trigger-for-an-adc-and-fpga/39471).

Sincerely,

Aaron

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