-- The top level module in the I2S AXI Stream interface library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity i2s_axis_v1_0 is generic ( -- Users to add parameters here I2S_DATA_WIDTH : integer := 24; -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Master Bus Interface I2S_L_RECV_AXIS C_I2S_L_RECV_AXIS_TDATA_WIDTH : integer := 32; C_I2S_L_RECV_AXIS_START_COUNT : integer := 32; -- Parameters of Axi Master Bus Interface I2S_R_RECV_AXIS C_I2S_R_RECV_AXIS_TDATA_WIDTH : integer := 32; C_I2S_R_RECV_AXIS_START_COUNT : integer := 32; -- Parameters of Axi Slave Bus Interface I2S_L_SEND_AXIS C_I2S_L_SEND_AXIS_TDATA_WIDTH : integer := 32; -- Parameters of Axi Slave Bus Interface I2S_R_SEND_AXIS C_I2S_R_SEND_AXIS_TDATA_WIDTH : integer := 32 ); port ( -- Users to add ports here i2s_mclk : in std_logic; i2s_bclk : out std_logic; i2s_lrck : out std_logic; i2s_sdin : in std_logic; i2s_sdout : out std_logic; i2s_m_axis_aclk : in std_logic; i2s_m_axis_aresetn : in std_logic; -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Master Bus Interface I2S_L_RECV_AXIS i2s_l_recv_axis_tvalid : out std_logic; i2s_l_recv_axis_tdata : out std_logic_vector(C_I2S_L_RECV_AXIS_TDATA_WIDTH-1 downto 0); i2s_l_recv_axis_tready : in std_logic; -- Ports of Axi Master Bus Interface I2S_R_RECV_AXIS i2s_r_recv_axis_tvalid : out std_logic; i2s_r_recv_axis_tdata : out std_logic_vector(C_I2S_R_RECV_AXIS_TDATA_WIDTH-1 downto 0); i2s_r_recv_axis_tready : in std_logic; -- Ports of Axi Slave Bus Interface I2S_L_SEND_AXIS i2s_l_send_axis_tready : out std_logic; i2s_l_send_axis_tdata : in std_logic_vector(C_I2S_L_SEND_AXIS_TDATA_WIDTH-1 downto 0); i2s_l_send_axis_tvalid : in std_logic; -- Ports of Axi Slave Bus Interface I2S_R_SEND_AXIS i2s_r_send_axis_tready : out std_logic; i2s_r_send_axis_tdata : in std_logic_vector(C_I2S_R_SEND_AXIS_TDATA_WIDTH-1 downto 0); i2s_r_send_axis_tvalid : in std_logic ); end i2s_axis_v1_0; architecture arch_imp of i2s_axis_v1_0 is -- component declaration component i2s_axis_v1_0_I2S_L_RECV_AXIS is generic ( I2S_DATA_WIDTH : integer := 24; C_M_AXIS_TDATA_WIDTH : integer := 32 ); port ( I2S_L_RECV : in std_logic_vector(I2S_DATA_WIDTH-1 downto 0); I2S_DONE : in std_logic; I2S_LR_DONE : in std_logic; M_AXIS_ACLK : in std_logic; M_AXIS_ARESETN : in std_logic; M_AXIS_TVALID : out std_logic; M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0); M_AXIS_TREADY : in std_logic ); end component i2s_axis_v1_0_I2S_L_RECV_AXIS; component i2s_axis_v1_0_I2S_R_RECV_AXIS is generic ( I2S_DATA_WIDTH : integer := 24; C_M_AXIS_TDATA_WIDTH : integer := 32 ); port ( I2S_R_RECV : in std_logic_vector(I2S_DATA_WIDTH-1 downto 0); I2S_DONE : in std_logic; I2S_LR_DONE : in std_logic; M_AXIS_ACLK : in std_logic; M_AXIS_ARESETN : in std_logic; M_AXIS_TVALID : out std_logic; M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0); M_AXIS_TREADY : in std_logic ); end component i2s_axis_v1_0_I2S_R_RECV_AXIS; component i2s_axis_v1_0_I2S_L_SEND_AXIS is generic ( I2S_DATA_WIDTH : integer := 24; C_S_AXIS_TDATA_WIDTH : integer := 32 ); port ( I2S_L_SEND : out std_logic_vector(I2S_DATA_WIDTH-1 downto 0); I2S_DONE : in std_logic; I2S_LR_DONE : in std_logic; S_AXIS_ACLK : in std_logic; S_AXIS_ARESETN : in std_logic; S_AXIS_TREADY : out std_logic; S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0); S_AXIS_TVALID : in std_logic ); end component i2s_axis_v1_0_I2S_L_SEND_AXIS; component i2s_axis_v1_0_I2S_R_SEND_AXIS is generic ( I2S_DATA_WIDTH : integer := 24; C_S_AXIS_TDATA_WIDTH : integer := 32 ); port ( I2S_R_SEND : out std_logic_vector(I2S_DATA_WIDTH-1 downto 0); I2S_DONE : in std_logic; I2S_LR_DONE : in std_logic; S_AXIS_ACLK : in std_logic; S_AXIS_ARESETN : in std_logic; S_AXIS_TREADY : out std_logic; S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0); S_AXIS_TVALID : in std_logic ); end component i2s_axis_v1_0_I2S_R_SEND_AXIS; component i2s_interface is generic ( MCLK_FACTOR : integer := 8; -- Frequency of MCLK / Frequency of BCLK data_width : integer := 32 ); port ( -- Clock I/O MCLK : in std_logic; BCLK : out std_logic; LRCK : out std_logic; RESET : in std_logic; -- Serial data in SDIN : in std_logic; -- Parallel data inputs -- Maybe rename these? Kind of confusing. L_IN : in std_logic_vector(data_width-1 downto 0); R_IN : in std_logic_vector(data_width-1 downto 0); -- Serial data outputs SDOUT : out std_logic; -- Parallel data outputs L_OUT : out std_logic_vector(data_width-1 downto 0); R_OUT : out std_logic_vector(data_width-1 downto 0); -- Transfer complete signal LR_DONE : out std_logic; -- Just indicates which channel is finished. DONE : out std_logic ); end component i2s_interface; signal s_i2s_lr_done : std_logic; signal s_i2s_done : std_logic; signal s_i2s_l_recv : std_logic_vector(I2S_DATA_WIDTH-1 downto 0); signal s_i2s_r_recv : std_logic_vector(I2S_DATA_WIDTH-1 downto 0); signal s_i2s_l_send : std_logic_vector(I2S_DATA_WIDTH-1 downto 0); signal s_i2s_r_send : std_logic_vector(I2S_DATA_WIDTH-1 downto 0); begin -- Instantiation of Axi Bus Interface I2S_L_RECV_AXIS i2s_axis_v1_0_I2S_L_RECV_AXIS_inst : i2s_axis_v1_0_I2S_L_RECV_AXIS generic map ( I2S_DATA_WIDTH => I2S_DATA_WIDTH, C_M_AXIS_TDATA_WIDTH => C_I2S_L_RECV_AXIS_TDATA_WIDTH ) port map ( I2S_L_RECV => s_i2s_l_recv, I2S_DONE => s_i2s_done, I2S_LR_DONE => s_i2s_lr_done, M_AXIS_ACLK => i2s_m_axis_aclk, M_AXIS_ARESETN => i2s_m_axis_aresetn, M_AXIS_TVALID => i2s_l_recv_axis_tvalid, M_AXIS_TDATA => i2s_l_recv_axis_tdata, M_AXIS_TREADY => i2s_l_recv_axis_tready ); -- Instantiation of Axi Bus Interface I2S_R_RECV_AXIS i2s_axis_v1_0_I2S_R_RECV_AXIS_inst : i2s_axis_v1_0_I2S_R_RECV_AXIS generic map ( I2S_DATA_WIDTH => I2S_DATA_WIDTH, C_M_AXIS_TDATA_WIDTH => C_I2S_R_RECV_AXIS_TDATA_WIDTH ) port map ( I2S_R_RECV => s_i2s_r_recv, I2S_DONE => s_i2s_done, I2S_LR_DONE => s_i2s_lr_done, M_AXIS_ACLK => i2s_m_axis_aclk, M_AXIS_ARESETN => i2s_m_axis_aresetn, M_AXIS_TVALID => i2s_r_recv_axis_tvalid, M_AXIS_TDATA => i2s_r_recv_axis_tdata, M_AXIS_TREADY => i2s_r_recv_axis_tready ); -- Instantiation of Axi Bus Interface I2S_L_SEND_AXIS i2s_axis_v1_0_I2S_L_SEND_AXIS_inst : i2s_axis_v1_0_I2S_L_SEND_AXIS generic map ( I2S_DATA_WIDTH => I2S_DATA_WIDTH, C_S_AXIS_TDATA_WIDTH => C_I2S_L_SEND_AXIS_TDATA_WIDTH ) port map ( I2S_L_SEND => s_i2s_l_send, I2S_DONE => s_i2s_done, I2S_LR_DONE => s_i2s_lr_done, S_AXIS_ACLK => i2s_m_axis_aclk, S_AXIS_ARESETN => i2s_m_axis_aresetn, S_AXIS_TREADY => i2s_l_send_axis_tready, S_AXIS_TDATA => i2s_l_send_axis_tdata, S_AXIS_TVALID => i2s_l_send_axis_tvalid ); -- Instantiation of Axi Bus Interface I2S_R_SEND_AXIS i2s_axis_v1_0_I2S_R_SEND_AXIS_inst : i2s_axis_v1_0_I2S_R_SEND_AXIS generic map ( I2S_DATA_WIDTH => I2S_DATA_WIDTH, C_S_AXIS_TDATA_WIDTH => C_I2S_R_SEND_AXIS_TDATA_WIDTH ) port map ( I2S_R_SEND => s_i2s_r_send, I2S_DONE => s_i2s_done, I2S_LR_DONE => s_i2s_lr_done, S_AXIS_ACLK => i2s_m_axis_aclk, S_AXIS_ARESETN => i2s_m_axis_aresetn, S_AXIS_TREADY => i2s_r_send_axis_tready, S_AXIS_TDATA => i2s_r_send_axis_tdata, S_AXIS_TVALID => i2s_r_send_axis_tvalid ); -- Add user logic here i2s_inst : i2s_interface generic map ( MCLK_FACTOR => 8, data_width => I2S_DATA_WIDTH ) port map ( MCLK => i2s_mclk, BCLK => i2s_bclk, LRCK => i2s_lrck, RESET => i2s_m_axis_aresetn, SDIN => i2s_sdin, L_IN => s_i2s_l_send, R_IN => s_i2s_r_send, SDOUT => i2s_sdout, L_OUT => s_i2s_l_recv, R_OUT => s_i2s_r_recv, LR_DONE => s_i2s_lr_done, DONE => s_i2s_done ); -- User logic ends end arch_imp;