Static Timing Analysis

Project : CY8CKIT_003_TX
Build Time : 10/15/13 11:58:23
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
RadioController_IntClock CyMASTER_CLK 2.000 MHz 2.000 MHz 65.355 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\RadioController:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \RadioController:BSPIM:RxStsReg\/status_6 65.355 MHz 15.301 484.699
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,2) 1 \RadioController:BSPIM:sR8:Dp:u0\ \RadioController:BSPIM:sR8:Dp:u0\/clock \RadioController:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 5.280
Route 1 \RadioController:BSPIM:rx_status_4\ \RadioController:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \RadioController:BSPIM:rx_status_6\/main_5 2.796
macrocell16 U(3,2) 1 \RadioController:BSPIM:rx_status_6\ \RadioController:BSPIM:rx_status_6\/main_5 \RadioController:BSPIM:rx_status_6\/q 3.350
Route 1 \RadioController:BSPIM:rx_status_6\ \RadioController:BSPIM:rx_status_6\/q \RadioController:BSPIM:RxStsReg\/status_6 2.305
statusicell1 U(3,2) 1 \RadioController:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\RadioController:BSPIM:sR8:Dp:u0\/so_comb Net_23/main_4 70.837 MHz 14.117 485.883
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,2) 1 \RadioController:BSPIM:sR8:Dp:u0\ \RadioController:BSPIM:sR8:Dp:u0\/clock \RadioController:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \RadioController:BSPIM:mosi_from_dp\ \RadioController:BSPIM:sR8:Dp:u0\/so_comb Net_23/main_4 2.307
macrocell10 U(2,2) 1 Net_23 SETUP 3.510
Clock Skew 0.000
\RadioController:BSPIM:BitCounter\/count_0 \RadioController:BSPIM:TxStsReg\/status_3 72.664 MHz 13.762 486.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ \RadioController:BSPIM:BitCounter\/clock \RadioController:BSPIM:BitCounter\/count_0 2.110
Route 1 \RadioController:BSPIM:count_0\ \RadioController:BSPIM:BitCounter\/count_0 \RadioController:BSPIM:load_rx_data\/main_4 3.320
macrocell15 U(2,2) 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/main_4 \RadioController:BSPIM:load_rx_data\/q 3.350
Route 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/q \RadioController:BSPIM:TxStsReg\/status_3 3.412
statusicell2 U(2,3) 1 \RadioController:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\RadioController:BSPIM:BitCounter\/count_2 \RadioController:BSPIM:TxStsReg\/status_3 72.886 MHz 13.720 486.280
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ \RadioController:BSPIM:BitCounter\/clock \RadioController:BSPIM:BitCounter\/count_2 2.110
Route 1 \RadioController:BSPIM:count_2\ \RadioController:BSPIM:BitCounter\/count_2 \RadioController:BSPIM:load_rx_data\/main_2 3.278
macrocell15 U(2,2) 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/main_2 \RadioController:BSPIM:load_rx_data\/q 3.350
Route 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/q \RadioController:BSPIM:TxStsReg\/status_3 3.412
statusicell2 U(2,3) 1 \RadioController:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\RadioController:BSPIM:BitCounter\/count_1 \RadioController:BSPIM:TxStsReg\/status_3 72.924 MHz 13.713 486.287
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ \RadioController:BSPIM:BitCounter\/clock \RadioController:BSPIM:BitCounter\/count_1 2.110
Route 1 \RadioController:BSPIM:count_1\ \RadioController:BSPIM:BitCounter\/count_1 \RadioController:BSPIM:load_rx_data\/main_3 3.271
macrocell15 U(2,2) 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/main_3 \RadioController:BSPIM:load_rx_data\/q 3.350
Route 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/q \RadioController:BSPIM:TxStsReg\/status_3 3.412
statusicell2 U(2,3) 1 \RadioController:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\RadioController:BSPIM:BitCounter\/count_3 \RadioController:BSPIM:TxStsReg\/status_3 74.582 MHz 13.408 486.592
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ \RadioController:BSPIM:BitCounter\/clock \RadioController:BSPIM:BitCounter\/count_3 2.110
Route 1 \RadioController:BSPIM:count_3\ \RadioController:BSPIM:BitCounter\/count_3 \RadioController:BSPIM:load_rx_data\/main_1 2.966
macrocell15 U(2,2) 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/main_1 \RadioController:BSPIM:load_rx_data\/q 3.350
Route 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/q \RadioController:BSPIM:TxStsReg\/status_3 3.412
statusicell2 U(2,3) 1 \RadioController:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\RadioController:BSPIM:BitCounter\/count_4 \RadioController:BSPIM:TxStsReg\/status_3 74.605 MHz 13.404 486.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ \RadioController:BSPIM:BitCounter\/clock \RadioController:BSPIM:BitCounter\/count_4 2.110
Route 1 \RadioController:BSPIM:count_4\ \RadioController:BSPIM:BitCounter\/count_4 \RadioController:BSPIM:load_rx_data\/main_0 2.962
macrocell15 U(2,2) 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/main_0 \RadioController:BSPIM:load_rx_data\/q 3.350
Route 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/q \RadioController:BSPIM:TxStsReg\/status_3 3.412
statusicell2 U(2,3) 1 \RadioController:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\RadioController:BSPIM:BitCounter\/count_0 \RadioController:BSPIM:sR8:Dp:u0\/f1_load 75.335 MHz 13.274 486.726
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ \RadioController:BSPIM:BitCounter\/clock \RadioController:BSPIM:BitCounter\/count_0 2.110
Route 1 \RadioController:BSPIM:count_0\ \RadioController:BSPIM:BitCounter\/count_0 \RadioController:BSPIM:load_rx_data\/main_4 3.320
macrocell15 U(2,2) 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/main_4 \RadioController:BSPIM:load_rx_data\/q 3.350
Route 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/q \RadioController:BSPIM:sR8:Dp:u0\/f1_load 2.644
datapathcell1 U(2,2) 1 \RadioController:BSPIM:sR8:Dp:u0\ SETUP 1.850
Clock Skew 0.000
\RadioController:BSPIM:BitCounter\/count_2 \RadioController:BSPIM:sR8:Dp:u0\/f1_load 75.574 MHz 13.232 486.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ \RadioController:BSPIM:BitCounter\/clock \RadioController:BSPIM:BitCounter\/count_2 2.110
Route 1 \RadioController:BSPIM:count_2\ \RadioController:BSPIM:BitCounter\/count_2 \RadioController:BSPIM:load_rx_data\/main_2 3.278
macrocell15 U(2,2) 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/main_2 \RadioController:BSPIM:load_rx_data\/q 3.350
Route 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/q \RadioController:BSPIM:sR8:Dp:u0\/f1_load 2.644
datapathcell1 U(2,2) 1 \RadioController:BSPIM:sR8:Dp:u0\ SETUP 1.850
Clock Skew 0.000
\RadioController:BSPIM:BitCounter\/count_1 \RadioController:BSPIM:sR8:Dp:u0\/f1_load 75.614 MHz 13.225 486.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ \RadioController:BSPIM:BitCounter\/clock \RadioController:BSPIM:BitCounter\/count_1 2.110
Route 1 \RadioController:BSPIM:count_1\ \RadioController:BSPIM:BitCounter\/count_1 \RadioController:BSPIM:load_rx_data\/main_3 3.271
macrocell15 U(2,2) 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/main_3 \RadioController:BSPIM:load_rx_data\/q 3.350
Route 1 \RadioController:BSPIM:load_rx_data\ \RadioController:BSPIM:load_rx_data\/q \RadioController:BSPIM:sR8:Dp:u0\/f1_load 2.644
datapathcell1 U(2,2) 1 \RadioController:BSPIM:sR8:Dp:u0\ SETUP 1.850
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\RadioController:BSPIM:load_cond\/q \RadioController:BSPIM:load_cond\/main_8 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(3,2) 1 \RadioController:BSPIM:load_cond\ \RadioController:BSPIM:load_cond\/clock_0 \RadioController:BSPIM:load_cond\/q 1.250
macrocell14 U(3,2) 1 \RadioController:BSPIM:load_cond\ \RadioController:BSPIM:load_cond\/q \RadioController:BSPIM:load_cond\/main_8 2.292
macrocell14 U(3,2) 1 \RadioController:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
Net_12/q Net_12/main_3 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(3,2) 1 Net_12 Net_12/clock_0 Net_12/q 1.250
macrocell1 U(3,2) 1 Net_12 Net_12/q Net_12/main_3 2.308
macrocell1 U(3,2) 1 Net_12 HOLD 0.000
Clock Skew 0.000
\RadioController:BSPIM:ld_ident\/q Net_23/main_10 3.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,2) 1 \RadioController:BSPIM:ld_ident\ \RadioController:BSPIM:ld_ident\/clock_0 \RadioController:BSPIM:ld_ident\/q 1.250
Route 1 \RadioController:BSPIM:ld_ident\ \RadioController:BSPIM:ld_ident\/q Net_23/main_10 2.600
macrocell10 U(2,2) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\RadioController:BSPIM:ld_ident\/q \RadioController:BSPIM:ld_ident\/main_8 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,2) 1 \RadioController:BSPIM:ld_ident\ \RadioController:BSPIM:ld_ident\/clock_0 \RadioController:BSPIM:ld_ident\/q 1.250
macrocell13 U(2,2) 1 \RadioController:BSPIM:ld_ident\ \RadioController:BSPIM:ld_ident\/q \RadioController:BSPIM:ld_ident\/main_8 2.601
macrocell13 U(2,2) 1 \RadioController:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\RadioController:BSPIM:ld_ident\/q \RadioController:BSPIM:state_1\/main_9 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,2) 1 \RadioController:BSPIM:ld_ident\ \RadioController:BSPIM:ld_ident\/clock_0 \RadioController:BSPIM:ld_ident\/q 1.250
Route 1 \RadioController:BSPIM:ld_ident\ \RadioController:BSPIM:ld_ident\/q \RadioController:BSPIM:state_1\/main_9 2.601
macrocell18 U(2,2) 1 \RadioController:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\RadioController:BSPIM:ld_ident\/q \RadioController:BSPIM:state_2\/main_9 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,2) 1 \RadioController:BSPIM:ld_ident\ \RadioController:BSPIM:ld_ident\/clock_0 \RadioController:BSPIM:ld_ident\/q 1.250
Route 1 \RadioController:BSPIM:ld_ident\ \RadioController:BSPIM:ld_ident\/q \RadioController:BSPIM:state_2\/main_9 2.601
macrocell19 U(2,2) 1 \RadioController:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\RadioController:BSPIM:cnt_enable\/q \RadioController:BSPIM:cnt_enable\/main_3 4.028
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 \RadioController:BSPIM:cnt_enable\ \RadioController:BSPIM:cnt_enable\/clock_0 \RadioController:BSPIM:cnt_enable\/q 1.250
macrocell12 U(3,2) 1 \RadioController:BSPIM:cnt_enable\ \RadioController:BSPIM:cnt_enable\/q \RadioController:BSPIM:cnt_enable\/main_3 2.778
macrocell12 U(3,2) 1 \RadioController:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\RadioController:BSPIM:cnt_enable\/q \RadioController:BSPIM:BitCounter\/enable 4.044
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,2) 1 \RadioController:BSPIM:cnt_enable\ \RadioController:BSPIM:cnt_enable\/clock_0 \RadioController:BSPIM:cnt_enable\/q 1.250
Route 1 \RadioController:BSPIM:cnt_enable\ \RadioController:BSPIM:cnt_enable\/q \RadioController:BSPIM:BitCounter\/enable 2.794
count7cell U(2,2) 1 \RadioController:BSPIM:BitCounter\ HOLD 0.000
Clock Skew 0.000
\RadioController:BSPIM:state_0\/q Net_12/main_2 4.633
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,2) 1 \RadioController:BSPIM:state_0\ \RadioController:BSPIM:state_0\/clock_0 \RadioController:BSPIM:state_0\/q 1.250
Route 1 \RadioController:BSPIM:state_0\ \RadioController:BSPIM:state_0\/q Net_12/main_2 3.383
macrocell1 U(3,2) 1 Net_12 HOLD 0.000
Clock Skew 0.000
\RadioController:BSPIM:state_0\/q \RadioController:BSPIM:cnt_enable\/main_2 4.633
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,2) 1 \RadioController:BSPIM:state_0\ \RadioController:BSPIM:state_0\/clock_0 \RadioController:BSPIM:state_0\/q 1.250
Route 1 \RadioController:BSPIM:state_0\ \RadioController:BSPIM:state_0\/q \RadioController:BSPIM:cnt_enable\/main_2 3.383
macrocell12 U(3,2) 1 \RadioController:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ RadioController_IntClock
Source Destination Delay (ns)
MISO(0)_PAD \RadioController:BSPIM:sR8:Dp:u0\/route_si 21.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO(0)_PAD MISO(0)_PAD MISO(0)/pad_in 0.000
iocell10 P1[4] 1 MISO(0) MISO(0)/pad_in MISO(0)/fb 7.503
Route 1 Net_19 MISO(0)/fb \RadioController:BSPIM:sR8:Dp:u0\/route_si 7.414
datapathcell1 U(2,2) 1 \RadioController:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Clock path delay 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\LED_Control_Reg:Sync:ctrl_reg\/control_5 LED_5(0)_PAD 31.469
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \LED_Control_Reg:Sync:ctrl_reg\ \LED_Control_Reg:Sync:ctrl_reg\/busclk \LED_Control_Reg:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_62_5 \LED_Control_Reg:Sync:ctrl_reg\/control_5 Net_157_5/main_0 2.317
macrocell7 U(2,3) 1 Net_157_5 Net_157_5/main_0 Net_157_5/q 3.350
Route 1 Net_157_5 Net_157_5/q LED_5(0)/pin_input 7.484
iocell7 P2[2] 1 LED_5(0) LED_5(0)/pin_input LED_5(0)/pad_out 15.738
Route 1 LED_5(0)_PAD LED_5(0)/pad_out LED_5(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Control_Reg:Sync:ctrl_reg\/control_4 LED_4(0)_PAD 31.449
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \LED_Control_Reg:Sync:ctrl_reg\ \LED_Control_Reg:Sync:ctrl_reg\/busclk \LED_Control_Reg:Sync:ctrl_reg\/control_4 2.580
Route 1 Net_62_4 \LED_Control_Reg:Sync:ctrl_reg\/control_4 Net_157_4/main_0 2.320
macrocell6 U(2,3) 1 Net_157_4 Net_157_4/main_0 Net_157_4/q 3.350
Route 1 Net_157_4 Net_157_4/q LED_4(0)/pin_input 7.531
iocell6 P2[3] 1 LED_4(0) LED_4(0)/pin_input LED_4(0)/pad_out 15.668
Route 1 LED_4(0)_PAD LED_4(0)/pad_out LED_4(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Control_Reg:Sync:ctrl_reg\/control_2 LED_2(0)_PAD 31.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \LED_Control_Reg:Sync:ctrl_reg\ \LED_Control_Reg:Sync:ctrl_reg\/busclk \LED_Control_Reg:Sync:ctrl_reg\/control_2 2.580
Route 1 Net_62_2 \LED_Control_Reg:Sync:ctrl_reg\/control_2 Net_157_2/main_0 2.337
macrocell4 U(3,3) 1 Net_157_2 Net_157_2/main_0 Net_157_2/q 3.350
Route 1 Net_157_2 Net_157_2/q LED_2(0)/pin_input 7.439
iocell4 P4[1] 1 LED_2(0) LED_2(0)/pin_input LED_2(0)/pad_out 15.606
Route 1 LED_2(0)_PAD LED_2(0)/pad_out LED_2(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Control_Reg:Sync:ctrl_reg\/control_6 LED_6(0)_PAD 30.905
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \LED_Control_Reg:Sync:ctrl_reg\ \LED_Control_Reg:Sync:ctrl_reg\/busclk \LED_Control_Reg:Sync:ctrl_reg\/control_6 2.580
Route 1 Net_62_6 \LED_Control_Reg:Sync:ctrl_reg\/control_6 Net_157_6/main_0 2.303
macrocell8 U(2,3) 1 Net_157_6 Net_157_6/main_0 Net_157_6/q 3.350
Route 1 Net_157_6 Net_157_6/q LED_6(0)/pin_input 7.457
iocell8 P2[1] 1 LED_6(0) LED_6(0)/pin_input LED_6(0)/pad_out 15.215
Route 1 LED_6(0)_PAD LED_6(0)/pad_out LED_6(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Control_Reg:Sync:ctrl_reg\/control_7 LED_7(0)_PAD 30.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \LED_Control_Reg:Sync:ctrl_reg\ \LED_Control_Reg:Sync:ctrl_reg\/busclk \LED_Control_Reg:Sync:ctrl_reg\/control_7 2.580
Route 1 Net_62_7 \LED_Control_Reg:Sync:ctrl_reg\/control_7 Net_157_7/main_0 2.333
macrocell9 U(2,3) 1 Net_157_7 Net_157_7/main_0 Net_157_7/q 3.350
Route 1 Net_157_7 Net_157_7/q LED_7(0)/pin_input 7.447
iocell9 P2[0] 1 LED_7(0) LED_7(0)/pin_input LED_7(0)/pad_out 15.168
Route 1 LED_7(0)_PAD LED_7(0)/pad_out LED_7(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Control_Reg:Sync:ctrl_reg\/control_1 LED_1(0)_PAD 30.612
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \LED_Control_Reg:Sync:ctrl_reg\ \LED_Control_Reg:Sync:ctrl_reg\/busclk \LED_Control_Reg:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_62_1 \LED_Control_Reg:Sync:ctrl_reg\/control_1 Net_157_1/main_0 2.311
macrocell3 U(2,3) 1 Net_157_1 Net_157_1/main_0 Net_157_1/q 3.350
Route 1 Net_157_1 Net_157_1/q LED_1(0)/pin_input 6.751
iocell3 P4[2] 1 LED_1(0) LED_1(0)/pin_input LED_1(0)/pad_out 15.620
Route 1 LED_1(0)_PAD LED_1(0)/pad_out LED_1(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Control_Reg:Sync:ctrl_reg\/control_0 LED_0(0)_PAD 30.263
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \LED_Control_Reg:Sync:ctrl_reg\ \LED_Control_Reg:Sync:ctrl_reg\/busclk \LED_Control_Reg:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_62_0 \LED_Control_Reg:Sync:ctrl_reg\/control_0 Net_157_0/main_0 2.308
macrocell2 U(2,3) 1 Net_157_0 Net_157_0/main_0 Net_157_0/q 3.350
Route 1 Net_157_0 Net_157_0/q LED_0(0)/pin_input 6.615
iocell2 P4[3] 1 LED_0(0) LED_0(0)/pin_input LED_0(0)/pad_out 15.410
Route 1 LED_0(0)_PAD LED_0(0)/pad_out LED_0(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Control_Reg:Sync:ctrl_reg\/control_3 LED_3(0)_PAD 30.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \LED_Control_Reg:Sync:ctrl_reg\ \LED_Control_Reg:Sync:ctrl_reg\/busclk \LED_Control_Reg:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_62_3 \LED_Control_Reg:Sync:ctrl_reg\/control_3 Net_157_3/main_0 2.339
macrocell5 U(3,3) 1 Net_157_3 Net_157_3/main_0 Net_157_3/q 3.350
Route 1 Net_157_3 Net_157_3/q LED_3(0)/pin_input 6.632
iocell5 P4[0] 1 LED_3(0) LED_3(0)/pin_input LED_3(0)/pad_out 15.150
Route 1 LED_3(0)_PAD LED_3(0)/pad_out LED_3(0)_PAD 0.000
Clock Clock path delay 0.000
+ RadioController_IntClock
Source Destination Delay (ns)
Net_25/q SCLK(0)_PAD 25.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,3) 1 Net_25 Net_25/clock_0 Net_25/q 1.250
Route 1 Net_25 Net_25/q SCLK(0)/pin_input 9.085
iocell12 P5[0] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 15.449
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
Net_23/q MOSI(0)_PAD 23.069
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,2) 1 Net_23 Net_23/clock_0 Net_23/q 1.250
Route 1 Net_23 Net_23/q MOSI(0)/pin_input 6.935
iocell11 P12[0] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 14.884
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000