Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version1909853
date_generatedTue Apr 16 16:18:01 2019 os_platformWIN64
product_versionVivado v2017.2 (64-bit) project_id8277aa4556ff4c8c9a384072153ee44b
project_iteration2 random_id3ea73436e4675f2fab88a0a69bf74d67
registration_id3ea73436e4675f2fab88a0a69bf74d67 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-5300U CPU @ 2.30GHz cpu_speed2295 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram8.000 GB total_processors1

vivado_usage
java_command_handlers
addsources=3 autoconnecttarget=1 closeproject=1 coreview=2
customizecore=1 helpabout=1 launchprogramfpga=1 newproject=1
openhardwaremanager=2 openrecenttarget=1 recustomizecore=2 runbitgen=4
runimplementation=6 runsynthesis=4 showview=3 viewtaskimplementation=4
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=2 carry4=44 fdce=211 gnd=2
ibuf=3 lut1=35 lut2=169 lut3=48
lut4=1 lut5=2 lut6=2 obuf=7
plle2_adv=1 vcc=2
pre_unisim_transformation
bufg=2 carry4=44 fdce=211 gnd=2
ibuf=3 lut1=35 lut2=169 lut3=48
lut4=1 lut5=2 lut6=2 obuf=7
plle2_adv=1 vcc=2

ip_statistics
clk_wiz_v5_4_1_0/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=clk_wiz_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=PLL
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=false use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=1 plle2_adv_util_percentage=20.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=44
fdce_functional_category=Flop & Latch fdce_used=211 ibuf_functional_category=IO ibuf_used=3
lut1_functional_category=LUT lut1_used=4 lut2_functional_category=LUT lut2_used=169
lut3_functional_category=LUT lut3_used=48 lut4_functional_category=LUT lut4_used=1
lut5_functional_category=LUT lut5_used=2 lut6_functional_category=LUT lut6_used=2
obuf_functional_category=IO obuf_used=7 plle2_adv_functional_category=Clock plle2_adv_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=179 lut_as_logic_util_percentage=0.86
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=211 register_as_flip_flop_util_percentage=0.51
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=179 slice_luts_util_percentage=0.86
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=211 slice_registers_util_percentage=0.51
fully_used_lut_ff_pairs_fixed=0.51 fully_used_lut_ff_pairs_used=24 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=179 lut_as_logic_util_percentage=0.86
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=78
lut_ff_pairs_with_one_unused_lut_output_fixed=78 lut_ff_pairs_with_one_unused_lut_output_used=77 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=102 lut_flip_flop_pairs_util_percentage=0.49 slice_available=8150 slice_fixed=0
slice_used=70 slice_util_percentage=0.86 slicel_fixed=0 slicel_used=52
slicem_fixed=0 slicem_used=18 unique_control_sets_used=8 using_o5_and_o6_fixed=8
using_o5_and_o6_used=47 using_o5_output_only_fixed=47 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=132
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=219843 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=8
dsp=0 effort=2 estimated_expansions=154224 ff=211
global_clocks=2 high_fanout_nets=0 iob=10 lut=179
movable_instances=498 nets=594 pins=2670 pll=1
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=i2s_playback -verilog_define=default::[not_specified]
usage
elapsed=00:00:38s hls_ip=0 memory_gain=422.680MB memory_peak=659.313MB