-- N BIT D FLIP FLOP ------------------------------------------------------------------------------------ -- *********************************************************************** -- FileName: DFlipFlop.vhd -- FPGA: ECP2-70E -- IDE: Lattice Diamond version 2.0.1 -- -- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT -- INFRINGEMENT. -- -- Version History -- Version 1.0 10/25/2012 Tony Storey -- Initial Public Release -- N-bit D FLIP FLOP FOR GENERIC USE ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DFlipFlop_Nbit is Generic( W : integer := 18 -- data word width ); Port( clk : in STD_LOGIC; n_reset : in STD_LOGIC; ready : in STD_LOGIC; L_bus, R_bus : in STD_LOGIC_VECTOR( W-1 downto 0); L_bus_out, R_bus_out : out STD_LOGIC_VECTOR( W-1 downto 0) ); end DFlipFlop_Nbit; architecture arch of DFlipFlop_Nbit is begin process ( clk, n_reset, ready, L_bus, R_bus) begin if (clk'event and clk = '1') then if n_reset = '0' then L_bus_out <= (others => '0'); R_bus_out <= (others => '0'); elsif(ready = '1') then L_bus_out <= L_bus; R_bus_out <= R_bus; end if; end if; end process; end arch;