Static Timing Analysis

Project : Design12
Build Time : 10/12/15 09:57:07
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_theACLK(routed) ADC_theACLK(routed) 12.000 MHz 12.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 61.072 MHz
ADC_theACLK CyMASTER_CLK 12.000 MHz 12.000 MHz N/A
UART_1_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 48.952 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 61.072 MHz 16.374 25.293
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.301
macrocell10 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.244
datapathcell1 U(1,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 85.609 MHz 11.681 29.986
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.162
macrocell8 U(1,1) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_7 85.609 MHz 11.681 29.986
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_7 6.162
macrocell12 U(1,1) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 90.942 MHz 10.996 30.671
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.477
macrocell4 U(0,0) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_8 91.008 MHz 10.988 30.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_8 5.469
macrocell11 U(1,0) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_5 91.008 MHz 10.988 30.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_5 5.469
macrocell15 U(1,0) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 92.421 MHz 10.820 30.847
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.301
macrocell3 U(0,0) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 48.952 MHz 20.428 1062.905
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,2) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 7.347
macrocell2 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.291
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxSts\/status_0 50.287 MHz 19.886 1063.447
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,2) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_status_0\/main_1 8.910
macrocell22 U(1,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_1 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.876
statusicell2 U(1,2) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 52.320 MHz 19.113 1064.220
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_0 6.254
macrocell7 U(1,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.899
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 54.101 MHz 18.484 1064.849
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,2) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 5.403
macrocell2 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.291
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 54.963 MHz 18.194 1065.139
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,2) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 5.113
macrocell2 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.291
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_address_detected\/q \UART_1:BUART:sRX:RxBitCounter\/load 57.870 MHz 17.280 1066.053
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,2) 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/clock_0 \UART_1:BUART:rx_address_detected\/q 1.250
Route 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_counter_load\/main_3 4.421
macrocell7 U(1,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.899
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 58.268 MHz 17.162 1066.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_2 4.303
macrocell7 U(1,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.899
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxSts\/status_0 59.598 MHz 16.779 1066.554
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,2) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_status_0\/main_0 5.803
macrocell22 U(1,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_0 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.876
statusicell2 U(1,2) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.741 MHz 16.739 1066.594
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 4.718
macrocell2 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.291
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:TxSts\/status_0 60.038 MHz 16.656 1066.677
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,2) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_status_0\/main_4 5.680
macrocell22 U(1,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_4 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.876
statusicell2 U(1,2) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 7.310
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.301
macrocell3 U(0,0) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_8 7.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_8 5.469
macrocell11 U(1,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_5 7.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_5 5.469
macrocell15 U(1,0) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 7.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.477
macrocell4 U(0,0) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 8.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.162
macrocell8 U(1,1) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_7 8.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_7 6.162
macrocell12 U(1,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 12.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_16 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.301
macrocell10 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.244
datapathcell1 U(1,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 1.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.250
statusicell1 U(1,0) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.840
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.650
macrocell24 U(0,1) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.925
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART_1:BUART:rx_count_0\ \UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.305
macrocell6 U(1,1) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_2\/main_4 2.944
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_2\/main_4 2.324
macrocell12 U(1,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_5 2.945
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_5 2.325
macrocell12 U(1,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.951
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.331
macrocell6 U(1,1) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 3.268
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.648
macrocell6 U(1,1) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_6 3.277
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_6 2.657
macrocell12 U(1,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 3.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,0) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
macrocell3 U(0,0) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 2.232
macrocell3 U(0,0) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,1) 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/clock_0 \UART_1:BUART:rx_last\/q 1.250
Route 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 2.302
macrocell12 U(1,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 29.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,1) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_11/main_0 2.586
macrocell1 U(0,1) 1 Net_11 Net_11/main_0 Net_11/q 3.350
Route 1 Net_11 Net_11/q Tx_1(0)/pin_input 5.679
iocell4 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000