\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
57.389 MHz |
17.425 |
1065.908 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell10 |
U(1,1) |
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/clock_0 |
\UART_1:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:counter_load_not\/main_0 |
4.316 |
macrocell2 |
U(1,1) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_0 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.319 |
datapathcell2 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
60.794 MHz |
16.449 |
1066.884 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART_1:BUART:tx_bitclk_enable_pre\ |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART_1:BUART:counter_load_not\/main_2 |
4.400 |
macrocell2 |
U(1,1) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_2 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.319 |
datapathcell2 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
61.709 MHz |
16.205 |
1067.128 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell11 |
U(1,1) |
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/clock_0 |
\UART_1:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:counter_load_not\/main_1 |
3.096 |
macrocell2 |
U(1,1) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_1 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.319 |
datapathcell2 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
61.751 MHz |
16.194 |
1067.139 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell12 |
U(0,1) |
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/clock_0 |
\UART_1:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:counter_load_not\/main_3 |
3.085 |
macrocell2 |
U(1,1) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_3 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.319 |
datapathcell2 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_ctrl_mark_last\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
64.470 MHz |
15.511 |
1067.822 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell14 |
U(1,0) |
1 |
\UART_1:BUART:tx_ctrl_mark_last\ |
\UART_1:BUART:tx_ctrl_mark_last\/clock_0 |
\UART_1:BUART:tx_ctrl_mark_last\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_ctrl_mark_last\ |
\UART_1:BUART:tx_ctrl_mark_last\/q |
\UART_1:BUART:rx_counter_load\/main_0 |
3.302 |
macrocell5 |
U(0,0) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_0 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_0\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
65.240 MHz |
15.328 |
1068.005 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell15 |
U(0,0) |
1 |
\UART_1:BUART:rx_state_0\ |
\UART_1:BUART:rx_state_0\/clock_0 |
\UART_1:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_0\ |
\UART_1:BUART:rx_state_0\/q |
\UART_1:BUART:rx_counter_load\/main_1 |
3.119 |
macrocell5 |
U(0,0) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_1 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_2\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
65.846 MHz |
15.187 |
1068.146 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell18 |
U(0,0) |
1 |
\UART_1:BUART:rx_state_2\ |
\UART_1:BUART:rx_state_2\/clock_0 |
\UART_1:BUART:rx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_2\ |
\UART_1:BUART:rx_state_2\/q |
\UART_1:BUART:rx_counter_load\/main_3 |
2.978 |
macrocell5 |
U(0,0) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_3 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_3\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
66.397 MHz |
15.061 |
1068.272 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell17 |
U(0,0) |
1 |
\UART_1:BUART:rx_state_3\ |
\UART_1:BUART:rx_state_3\/clock_0 |
\UART_1:BUART:rx_state_3\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_3\ |
\UART_1:BUART:rx_state_3\/q |
\UART_1:BUART:rx_counter_load\/main_2 |
2.852 |
macrocell5 |
U(0,0) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_2 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:pollcount_0\/q |
\UART_1:BUART:sRX:RxShifter:u0\/route_si |
67.376 MHz |
14.842 |
1068.491 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell22 |
U(0,1) |
1 |
\UART_1:BUART:pollcount_0\ |
\UART_1:BUART:pollcount_0\/clock_0 |
\UART_1:BUART:pollcount_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:pollcount_0\ |
\UART_1:BUART:pollcount_0\/q |
\UART_1:BUART:rx_postpoll\/main_2 |
4.544 |
macrocell6 |
U(0,0) |
1 |
\UART_1:BUART:rx_postpoll\ |
\UART_1:BUART:rx_postpoll\/main_2 |
\UART_1:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_postpoll\ |
\UART_1:BUART:rx_postpoll\/q |
\UART_1:BUART:sRX:RxShifter:u0\/route_si |
2.228 |
datapathcell3 |
U(0,0) |
1 |
\UART_1:BUART:sRX:RxShifter:u0\ |
|
SETUP |
3.470 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:pollcount_1\/q |
\UART_1:BUART:sRX:RxShifter:u0\/route_si |
68.738 MHz |
14.548 |
1068.785 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell21 |
U(0,1) |
1 |
\UART_1:BUART:pollcount_1\ |
\UART_1:BUART:pollcount_1\/clock_0 |
\UART_1:BUART:pollcount_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:pollcount_1\ |
\UART_1:BUART:pollcount_1\/q |
\UART_1:BUART:rx_postpoll\/main_0 |
4.250 |
macrocell6 |
U(0,0) |
1 |
\UART_1:BUART:rx_postpoll\ |
\UART_1:BUART:rx_postpoll\/main_0 |
\UART_1:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_postpoll\ |
\UART_1:BUART:rx_postpoll\/q |
\UART_1:BUART:sRX:RxShifter:u0\/route_si |
2.228 |
datapathcell3 |
U(0,0) |
1 |
\UART_1:BUART:sRX:RxShifter:u0\ |
|
SETUP |
3.470 |
Clock |
|
|
|
|
Skew |
0.000 |
|