\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
48.952 MHz |
20.428 |
1062.905 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell19 |
U(0,2) |
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/clock_0 |
\UART_1:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:counter_load_not\/main_1 |
7.347 |
macrocell2 |
U(0,1) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_1 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.291 |
datapathcell3 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
50.287 MHz |
19.886 |
1063.447 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell19 |
U(0,2) |
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/clock_0 |
\UART_1:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_0\ |
\UART_1:BUART:tx_state_0\/q |
\UART_1:BUART:tx_status_0\/main_1 |
8.910 |
macrocell22 |
U(1,1) |
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/main_1 |
\UART_1:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
5.876 |
statusicell2 |
U(1,2) |
1 |
\UART_1:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_0\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
52.320 MHz |
19.113 |
1064.220 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell11 |
U(1,0) |
1 |
\UART_1:BUART:rx_state_0\ |
\UART_1:BUART:rx_state_0\/clock_0 |
\UART_1:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_0\ |
\UART_1:BUART:rx_state_0\/q |
\UART_1:BUART:rx_counter_load\/main_0 |
6.254 |
macrocell7 |
U(1,2) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_0 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.899 |
count7cell |
U(1,1) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
54.101 MHz |
18.484 |
1064.849 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell20 |
U(1,2) |
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/clock_0 |
\UART_1:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:counter_load_not\/main_0 |
5.403 |
macrocell2 |
U(0,1) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_0 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.291 |
datapathcell3 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
54.963 MHz |
18.194 |
1065.139 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell21 |
U(0,2) |
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/clock_0 |
\UART_1:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:counter_load_not\/main_3 |
5.113 |
macrocell2 |
U(0,1) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_3 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.291 |
datapathcell3 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_address_detected\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
57.870 MHz |
17.280 |
1066.053 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell5 |
U(1,2) |
1 |
\UART_1:BUART:rx_address_detected\ |
\UART_1:BUART:rx_address_detected\/clock_0 |
\UART_1:BUART:rx_address_detected\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_address_detected\ |
\UART_1:BUART:rx_address_detected\/q |
\UART_1:BUART:rx_counter_load\/main_3 |
4.421 |
macrocell7 |
U(1,2) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_3 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.899 |
count7cell |
U(1,1) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:rx_state_2\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
58.268 MHz |
17.162 |
1066.171 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell12 |
U(1,1) |
1 |
\UART_1:BUART:rx_state_2\ |
\UART_1:BUART:rx_state_2\/clock_0 |
\UART_1:BUART:rx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:rx_state_2\ |
\UART_1:BUART:rx_state_2\/q |
\UART_1:BUART:rx_counter_load\/main_2 |
4.303 |
macrocell7 |
U(1,2) |
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/main_2 |
\UART_1:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:rx_counter_load\ |
\UART_1:BUART:rx_counter_load\/q |
\UART_1:BUART:sRX:RxBitCounter\/load |
2.899 |
count7cell |
U(1,1) |
1 |
\UART_1:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
59.598 MHz |
16.779 |
1066.554 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell20 |
U(1,2) |
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/clock_0 |
\UART_1:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_1\ |
\UART_1:BUART:tx_state_1\/q |
\UART_1:BUART:tx_status_0\/main_0 |
5.803 |
macrocell22 |
U(1,1) |
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/main_0 |
\UART_1:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
5.876 |
statusicell2 |
U(1,2) |
1 |
\UART_1:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
59.741 MHz |
16.739 |
1066.594 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell3 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART_1:BUART:tx_bitclk_enable_pre\ |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART_1:BUART:counter_load_not\/main_2 |
4.718 |
macrocell2 |
U(0,1) |
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/main_2 |
\UART_1:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:counter_load_not\ |
\UART_1:BUART:counter_load_not\/q |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.291 |
datapathcell3 |
U(0,1) |
1 |
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
60.038 MHz |
16.656 |
1066.677 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell21 |
U(0,2) |
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/clock_0 |
\UART_1:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART_1:BUART:tx_state_2\ |
\UART_1:BUART:tx_state_2\/q |
\UART_1:BUART:tx_status_0\/main_4 |
5.680 |
macrocell22 |
U(1,1) |
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/main_4 |
\UART_1:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART_1:BUART:tx_status_0\ |
\UART_1:BUART:tx_status_0\/q |
\UART_1:BUART:sTX:TxSts\/status_0 |
5.876 |
statusicell2 |
U(1,2) |
1 |
\UART_1:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|