noveno_ensayo Project Status (04/25/2022 - 18:58:49)
Project File: noveno_ensayo.xise Parser Errors:
Module Name: noveno_ensayo Implementation State: Programming File Generated
Target Device: xc6slx16-2csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
75 Warnings (75 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 137 18,224 1%  
    Number used as Flip Flops 136      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 1      
Number of Slice LUTs 174 9,112 1%  
    Number used as logic 173 9,112 1%  
        Number using O6 output only 96      
        Number using O5 output only 15      
        Number using O5 and O6 62      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 58 2,278 2%  
Number of MUXCYs used 68 4,556 1%  
Number of LUT Flip Flop pairs used 184      
    Number with an unused Flip Flop 66 184 35%  
    Number with an unused LUT 10 184 5%  
    Number of fully used LUT-FF pairs 108 184 58%  
    Number of unique control sets 12      
    Number of slice register sites lost
        to control set restrictions
32 18,224 1%  
Number of bonded IOBs 6 232 2%  
    Number of LOCed IOBs 6 6 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 1 32 3%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.65      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Apr 25 18:58:19 2022075 Warnings (75 new)7 Infos (7 new)
Translation ReportCurrentMon Apr 25 18:58:23 2022000
Map ReportCurrentMon Apr 25 18:58:32 2022006 Infos (6 new)
Place and Route ReportCurrentMon Apr 25 18:58:38 2022003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Apr 25 18:58:42 2022004 Infos (4 new)
Bitgen ReportCurrentMon Apr 25 18:58:47 2022000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMon Apr 25 18:58:48 2022
WebTalk Log FileCurrentMon Apr 25 18:58:49 2022

Date Generated: 04/25/2022 - 18:58:49