--------------------------------------------------------------------------------
Lattice TRACE Report - Setup
Fri Jun 15 12:25:52 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design file:     Peripheral_Expansion_Top
Device,speed:    LCMXO2-1200ZE,1
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;
            30 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 

Passed: The following path meets requirements by 4.524ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I16/wb_dat_o_3  (from I16/wb_dat_o_0_sqmuxa +)
   Destination:    FF         Data in        I17/state_reg_3  (to clk_inferred_clock +)

   Delay:               6.404ns  (29.3% logic, 70.7% route), 2 logic levels.

 Constraint Details:

      6.404ns physical path delay SLICE_290 to SLICE_143 meets
     26.315ns delay constraint less
     14.955ns skew and
      0.432ns DIN_SET requirement (totaling 10.928ns) by 4.524ns

 Physical Path Details:

      Data path SLICE_290 to SLICE_143:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R4C8C.CLK to       R4C8C.Q0 SLICE_290 (from I16/wb_dat_o_0_sqmuxa)
ROUTE         3     4.526       R4C8C.Q0 to R7C12C.D0      wb_dat_o2mux_3
CTOF_DEL    ---     0.923      R7C12C.D0 to      R7C12C.F0 SLICE_143
ROUTE         1     0.000      R7C12C.F0 to R7C12C.DI0     I17/N_88s (to clk_inferred_clock)
                  --------
                    6.404   (29.3% logic, 70.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to SLICE_290:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R3C9C.CLK      clk_inferred_clock
REG_DEL     ---     0.955      R3C9C.CLK to       R3C9C.Q0 SLICE_145
ROUTE         4     4.146       R3C9C.Q0 to R4C11D.CLK     I17/state_reg_derived_clock_5
REG_DEL     ---     0.955     R4C11D.CLK to      R4C11D.Q0 SLICE_101
ROUTE        10     2.722      R4C11D.Q0 to R7C12B.D0      w_enable
CTOF_DEL    ---     0.923      R7C12B.D0 to      R7C12B.F0 I16/SLICE_289
ROUTE         5     5.254      R7C12B.F0 to R4C8C.CLK      I16/wb_dat_o_0_sqmuxa
                  --------
                   22.833   (12.4% logic, 87.6% route), 3 logic levels.

      Destination Clock Path OSCInst0 to SLICE_143:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R7C12C.CLK     clk_inferred_clock
                  --------
                    7.878   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 5.861ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I16/wb_adr_i_0  (from I16_state_reg_3 -)
   Destination:    EFB        Port           I15/EFBInst_0(ASIC)  (to clk_inferred_clock +)

   Delay:               6.556ns  (14.6% logic, 85.4% route), 1 logic levels.

 Constraint Details:

      6.556ns physical path delay SLICE_245 to I15/EFBInst_0 meets
     26.315ns delay constraint less
     11.710ns skew and
      2.188ns WBADRI_SET requirement (totaling 12.417ns) by 5.861ns

 Physical Path Details:

      Data path SLICE_245 to I15/EFBInst_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R3C8A.CLK to       R3C8A.Q0 SLICE_245 (from I16_state_reg_3)
ROUTE         1     5.601       R3C8A.Q0 to EFB.WBADRI0    wb_adr_i_0 (to clk_inferred_clock)
                  --------
                    6.556   (14.6% logic, 85.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to SLICE_245:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R3C9B.CLK      clk_inferred_clock
REG_DEL     ---     0.955      R3C9B.CLK to       R3C9B.Q0 I16/SLICE_136
ROUTE         6     4.685       R3C9B.Q0 to R7C12C.B1      I16/state_reg_0
CTOF_DEL    ---     0.923      R7C12C.B1 to      R7C12C.F1 SLICE_143
ROUTE        11     5.421      R7C12C.F1 to R3C8A.CLK      I16_state_reg_3
                  --------
                   19.862   (9.5% logic, 90.5% route), 2 logic levels.

      Destination Clock Path OSCInst0 to I15/EFBInst_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     8.152        OSC.OSC to EFB.WBCLKI     clk_inferred_clock
                  --------
                    8.152   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 6.546ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I16/wb_dat_o_3  (from I16/wb_dat_o_0_sqmuxa +)
   Destination:    FF         Data in        I17/state_reg_4  (to clk_inferred_clock +)

   Delay:               4.382ns  (42.9% logic, 57.1% route), 2 logic levels.

 Constraint Details:

      4.382ns physical path delay SLICE_290 to I17/SLICE_142 meets
     26.315ns delay constraint less
     14.955ns skew and
      0.432ns DIN_SET requirement (totaling 10.928ns) by 6.546ns

 Physical Path Details:

      Data path SLICE_290 to I17/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R4C8C.CLK to       R4C8C.Q0 SLICE_290 (from I16/wb_dat_o_0_sqmuxa)
ROUTE         3     2.504       R4C8C.Q0 to R4C9A.D0       wb_dat_o2mux_3
CTOF_DEL    ---     0.923       R4C9A.D0 to       R4C9A.F0 I17/SLICE_142
ROUTE         1     0.000       R4C9A.F0 to R4C9A.DI0      I17/N_87s (to clk_inferred_clock)
                  --------
                    4.382   (42.9% logic, 57.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to SLICE_290:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R3C9C.CLK      clk_inferred_clock
REG_DEL     ---     0.955      R3C9C.CLK to       R3C9C.Q0 SLICE_145
ROUTE         4     4.146       R3C9C.Q0 to R4C11D.CLK     I17/state_reg_derived_clock_5
REG_DEL     ---     0.955     R4C11D.CLK to      R4C11D.Q0 SLICE_101
ROUTE        10     2.722      R4C11D.Q0 to R7C12B.D0      w_enable
CTOF_DEL    ---     0.923      R7C12B.D0 to      R7C12B.F0 I16/SLICE_289
ROUTE         5     5.254      R7C12B.F0 to R4C8C.CLK      I16/wb_dat_o_0_sqmuxa
                  --------
                   22.833   (12.4% logic, 87.6% route), 3 logic levels.

      Destination Clock Path OSCInst0 to I17/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R4C9A.CLK      clk_inferred_clock
                  --------
                    7.878   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 6.744ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I16/wb_dat_i_4  (from I16_state_reg_3 -)
   Destination:    EFB        Port           I15/EFBInst_0(ASIC)  (to clk_inferred_clock +)

   Delay:               6.252ns  (15.3% logic, 84.7% route), 1 logic levels.

 Constraint Details:

      6.252ns physical path delay I16/SLICE_248 to I15/EFBInst_0 meets
     26.315ns delay constraint less
     11.710ns skew and
      1.609ns WBDATI_SET requirement (totaling 12.996ns) by 6.744ns

 Physical Path Details:

      Data path I16/SLICE_248 to I15/EFBInst_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R3C8C.CLK to       R3C8C.Q0 I16/SLICE_248 (from I16_state_reg_3)
ROUTE         2     5.297       R3C8C.Q0 to EFB.WBDATI4    wb_dat_i_4 (to clk_inferred_clock)
                  --------
                    6.252   (15.3% logic, 84.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I16/SLICE_248:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R3C9B.CLK      clk_inferred_clock
REG_DEL     ---     0.955      R3C9B.CLK to       R3C9B.Q0 I16/SLICE_136
ROUTE         6     4.685       R3C9B.Q0 to R7C12C.B1      I16/state_reg_0
CTOF_DEL    ---     0.923      R7C12C.B1 to      R7C12C.F1 SLICE_143
ROUTE        11     5.421      R7C12C.F1 to R3C8C.CLK      I16_state_reg_3
                  --------
                   19.862   (9.5% logic, 90.5% route), 2 logic levels.

      Destination Clock Path OSCInst0 to I15/EFBInst_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     8.152        OSC.OSC to EFB.WBCLKI     clk_inferred_clock
                  --------
                    8.152   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 6.915ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I16/wb_adr_i_1  (from I16_state_reg_3 -)
   Destination:    EFB        Port           I15/EFBInst_0(ASIC)  (to clk_inferred_clock +)

   Delay:               5.550ns  (17.2% logic, 82.8% route), 1 logic levels.

 Constraint Details:

      5.550ns physical path delay SLICE_245 to I15/EFBInst_0 meets
     26.315ns delay constraint less
     11.710ns skew and
      2.140ns WBADRI_SET requirement (totaling 12.465ns) by 6.915ns

 Physical Path Details:

      Data path SLICE_245 to I15/EFBInst_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R3C8A.CLK to       R3C8A.Q1 SLICE_245 (from I16_state_reg_3)
ROUTE         1     4.595       R3C8A.Q1 to EFB.WBADRI1    wb_adr_i_1 (to clk_inferred_clock)
                  --------
                    5.550   (17.2% logic, 82.8% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to SLICE_245:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R3C9B.CLK      clk_inferred_clock
REG_DEL     ---     0.955      R3C9B.CLK to       R3C9B.Q0 I16/SLICE_136
ROUTE         6     4.685       R3C9B.Q0 to R7C12C.B1      I16/state_reg_0
CTOF_DEL    ---     0.923      R7C12C.B1 to      R7C12C.F1 SLICE_143
ROUTE        11     5.421      R7C12C.F1 to R3C8A.CLK      I16_state_reg_3
                  --------
                   19.862   (9.5% logic, 90.5% route), 2 logic levels.

      Destination Clock Path OSCInst0 to I15/EFBInst_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     8.152        OSC.OSC to EFB.WBCLKI     clk_inferred_clock
                  --------
                    8.152   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.455ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I14/QEI_reg_2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I14/QEI_reg_15  (to clk_inferred_clock +)

   Delay:              18.428ns  (43.1% logic, 56.9% route), 11 logic levels.

 Constraint Details:

     18.428ns physical path delay I14/SLICE_25 to I14/SLICE_18 meets
     26.315ns delay constraint less
      0.000ns skew and
      0.432ns DIN_SET requirement (totaling 25.883ns) by 7.455ns

 Physical Path Details:

      Data path I14/SLICE_25 to I14/SLICE_18:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R5C6B.CLK to       R5C6B.Q1 I14/SLICE_25 (from clk_inferred_clock)
ROUTE         2     3.386       R5C6B.Q1 to R4C7C.B0       I14/QEI_reg_2
CTOF_DEL    ---     0.923       R4C7C.B0 to       R4C7C.F0 I14/SLICE_269
ROUTE         2     2.336       R4C7C.F0 to R4C7A.B0       I14/g0_0_8
CTOF_DEL    ---     0.923       R4C7A.B0 to       R4C7A.F0 I14/SLICE_268
ROUTE        17     4.758       R4C7A.F0 to R5C6B.B0       I14_op_le_un3_neg_cntlt15_i
C0TOFCO_DE  ---     2.064       R5C6B.B0 to      R5C6B.FCO I14/SLICE_25
ROUTE         1     0.000      R5C6B.FCO to R5C6C.FCI      I14/un1_QEI_reg_cry_2
FCITOFCO_D  ---     0.317      R5C6C.FCI to      R5C6C.FCO I14/SLICE_24
ROUTE         1     0.000      R5C6C.FCO to R5C6D.FCI      I14/un1_QEI_reg_cry_4
FCITOFCO_D  ---     0.317      R5C6D.FCI to      R5C6D.FCO I14/SLICE_23
ROUTE         1     0.000      R5C6D.FCO to R5C7A.FCI      I14/un1_QEI_reg_cry_6
FCITOFCO_D  ---     0.317      R5C7A.FCI to      R5C7A.FCO I14/SLICE_22
ROUTE         1     0.000      R5C7A.FCO to R5C7B.FCI      I14/un1_QEI_reg_cry_8
FCITOFCO_D  ---     0.317      R5C7B.FCI to      R5C7B.FCO I14/SLICE_21
ROUTE         1     0.000      R5C7B.FCO to R5C7C.FCI      I14/un1_QEI_reg_cry_10
FCITOFCO_D  ---     0.317      R5C7C.FCI to      R5C7C.FCO I14/SLICE_20
ROUTE         1     0.000      R5C7C.FCO to R5C7D.FCI      I14/un1_QEI_reg_cry_12
FCITOFCO_D  ---     0.317      R5C7D.FCI to      R5C7D.FCO I14/SLICE_19
ROUTE         1     0.000      R5C7D.FCO to R5C8A.FCI      I14/un1_QEI_reg_cry_14
FCITOF0_DE  ---     1.181      R5C8A.FCI to       R5C8A.F0 I14/SLICE_18
ROUTE         1     0.000       R5C8A.F0 to R5C8A.DI0      I14/bus_in_15 (to clk_inferred_clock)
                  --------
                   18.428   (43.1% logic, 56.9% route), 11 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I14/SLICE_25:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R5C6B.CLK      clk_inferred_clock
                  --------
                    7.878   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I14/SLICE_18:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R5C8A.CLK      clk_inferred_clock
                  --------
                    7.878   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.458ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I16/wb_dat_o_4  (from I16/wb_dat_o_0_sqmuxa +)
   Destination:    FF         Data in        I17/state_reg_1  (to clk_inferred_clock +)

   Delay:               3.470ns  (54.1% logic, 45.9% route), 2 logic levels.

 Constraint Details:

      3.470ns physical path delay SLICE_290 to I17/SLICE_141 meets
     26.315ns delay constraint less
     14.955ns skew and
      0.432ns DIN_SET requirement (totaling 10.928ns) by 7.458ns

 Physical Path Details:

      Data path SLICE_290 to I17/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R4C8C.CLK to       R4C8C.Q1 SLICE_290 (from I16/wb_dat_o_0_sqmuxa)
ROUTE         3     1.592       R4C8C.Q1 to R4C8B.D1       wb_dat_o2mux_4
CTOF_DEL    ---     0.923       R4C8B.D1 to       R4C8B.F1 I17/SLICE_141
ROUTE         1     0.000       R4C8B.F1 to R4C8B.DI1      I17/N_90s (to clk_inferred_clock)
                  --------
                    3.470   (54.1% logic, 45.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to SLICE_290:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R3C9C.CLK      clk_inferred_clock
REG_DEL     ---     0.955      R3C9C.CLK to       R3C9C.Q0 SLICE_145
ROUTE         4     4.146       R3C9C.Q0 to R4C11D.CLK     I17/state_reg_derived_clock_5
REG_DEL     ---     0.955     R4C11D.CLK to      R4C11D.Q0 SLICE_101
ROUTE        10     2.722      R4C11D.Q0 to R7C12B.D0      w_enable
CTOF_DEL    ---     0.923      R7C12B.D0 to      R7C12B.F0 I16/SLICE_289
ROUTE         5     5.254      R7C12B.F0 to R4C8C.CLK      I16/wb_dat_o_0_sqmuxa
                  --------
                   22.833   (12.4% logic, 87.6% route), 3 logic levels.

      Destination Clock Path OSCInst0 to I17/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R4C8B.CLK      clk_inferred_clock
                  --------
                    7.878   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.458ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I16/wb_dat_o_4  (from I16/wb_dat_o_0_sqmuxa +)
   Destination:    FF         Data in        I17/state_reg_0  (to clk_inferred_clock +)

   Delay:               3.470ns  (54.1% logic, 45.9% route), 2 logic levels.

 Constraint Details:

      3.470ns physical path delay SLICE_290 to I17/SLICE_141 meets
     26.315ns delay constraint less
     14.955ns skew and
      0.432ns DIN_SET requirement (totaling 10.928ns) by 7.458ns

 Physical Path Details:

      Data path SLICE_290 to I17/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R4C8C.CLK to       R4C8C.Q1 SLICE_290 (from I16/wb_dat_o_0_sqmuxa)
ROUTE         3     1.592       R4C8C.Q1 to R4C8B.D0       wb_dat_o2mux_4
CTOF_DEL    ---     0.923       R4C8B.D0 to       R4C8B.F0 I17/SLICE_141
ROUTE         1     0.000       R4C8B.F0 to R4C8B.DI0      I17/N_91s (to clk_inferred_clock)
                  --------
                    3.470   (54.1% logic, 45.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to SLICE_290:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R3C9C.CLK      clk_inferred_clock
REG_DEL     ---     0.955      R3C9C.CLK to       R3C9C.Q0 SLICE_145
ROUTE         4     4.146       R3C9C.Q0 to R4C11D.CLK     I17/state_reg_derived_clock_5
REG_DEL     ---     0.955     R4C11D.CLK to      R4C11D.Q0 SLICE_101
ROUTE        10     2.722      R4C11D.Q0 to R7C12B.D0      w_enable
CTOF_DEL    ---     0.923      R7C12B.D0 to      R7C12B.F0 I16/SLICE_289
ROUTE         5     5.254      R7C12B.F0 to R4C8C.CLK      I16/wb_dat_o_0_sqmuxa
                  --------
                   22.833   (12.4% logic, 87.6% route), 3 logic levels.

      Destination Clock Path OSCInst0 to I17/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R4C8B.CLK      clk_inferred_clock
                  --------
                    7.878   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.571ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I16/wb_we_i  (from I16_state_reg_3 -)
   Destination:    EFB        Port           I15/EFBInst_0(ASIC)  (to clk_inferred_clock +)

   Delay:               5.559ns  (17.2% logic, 82.8% route), 1 logic levels.

 Constraint Details:

      5.559ns physical path delay SLICE_255 to I15/EFBInst_0 meets
     26.315ns delay constraint less
     11.710ns skew and
      1.475ns WBWEI_SET requirement (totaling 13.130ns) by 7.571ns

 Physical Path Details:

      Data path SLICE_255 to I15/EFBInst_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R5C8D.CLK to       R5C8D.Q0 SLICE_255 (from I16_state_reg_3)
ROUTE         1     4.604       R5C8D.Q0 to EFB.WBWEI      wb_we_i (to clk_inferred_clock)
                  --------
                    5.559   (17.2% logic, 82.8% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to SLICE_255:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R3C9B.CLK      clk_inferred_clock
REG_DEL     ---     0.955      R3C9B.CLK to       R3C9B.Q0 I16/SLICE_136
ROUTE         6     4.685       R3C9B.Q0 to R7C12C.B1      I16/state_reg_0
CTOF_DEL    ---     0.923      R7C12C.B1 to      R7C12C.F1 SLICE_143
ROUTE        11     5.421      R7C12C.F1 to R5C8D.CLK      I16_state_reg_3
                  --------
                   19.862   (9.5% logic, 90.5% route), 2 logic levels.

      Destination Clock Path OSCInst0 to I15/EFBInst_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     8.152        OSC.OSC to EFB.WBCLKI     clk_inferred_clock
                  --------
                    8.152   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 7.629ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I14/QEI_reg_1  (from clk_inferred_clock +)
   Destination:    FF         Data in        I14/QEI_reg_15  (to clk_inferred_clock +)

   Delay:              18.254ns  (43.5% logic, 56.5% route), 11 logic levels.

 Constraint Details:

     18.254ns physical path delay I14/SLICE_25 to I14/SLICE_18 meets
     26.315ns delay constraint less
      0.000ns skew and
      0.432ns DIN_SET requirement (totaling 25.883ns) by 7.629ns

 Physical Path Details:

      Data path I14/SLICE_25 to I14/SLICE_18:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.955      R5C6B.CLK to       R5C6B.Q0 I14/SLICE_25 (from clk_inferred_clock)
ROUTE         2     3.212       R5C6B.Q0 to R4C7C.D0       I14/QEI_reg_1
CTOF_DEL    ---     0.923       R4C7C.D0 to       R4C7C.F0 I14/SLICE_269
ROUTE         2     2.336       R4C7C.F0 to R4C7A.B0       I14/g0_0_8
CTOF_DEL    ---     0.923       R4C7A.B0 to       R4C7A.F0 I14/SLICE_268
ROUTE        17     4.758       R4C7A.F0 to R5C6B.B0       I14_op_le_un3_neg_cntlt15_i
C0TOFCO_DE  ---     2.064       R5C6B.B0 to      R5C6B.FCO I14/SLICE_25
ROUTE         1     0.000      R5C6B.FCO to R5C6C.FCI      I14/un1_QEI_reg_cry_2
FCITOFCO_D  ---     0.317      R5C6C.FCI to      R5C6C.FCO I14/SLICE_24
ROUTE         1     0.000      R5C6C.FCO to R5C6D.FCI      I14/un1_QEI_reg_cry_4
FCITOFCO_D  ---     0.317      R5C6D.FCI to      R5C6D.FCO I14/SLICE_23
ROUTE         1     0.000      R5C6D.FCO to R5C7A.FCI      I14/un1_QEI_reg_cry_6
FCITOFCO_D  ---     0.317      R5C7A.FCI to      R5C7A.FCO I14/SLICE_22
ROUTE         1     0.000      R5C7A.FCO to R5C7B.FCI      I14/un1_QEI_reg_cry_8
FCITOFCO_D  ---     0.317      R5C7B.FCI to      R5C7B.FCO I14/SLICE_21
ROUTE         1     0.000      R5C7B.FCO to R5C7C.FCI      I14/un1_QEI_reg_cry_10
FCITOFCO_D  ---     0.317      R5C7C.FCI to      R5C7C.FCO I14/SLICE_20
ROUTE         1     0.000      R5C7C.FCO to R5C7D.FCI      I14/un1_QEI_reg_cry_12
FCITOFCO_D  ---     0.317      R5C7D.FCI to      R5C7D.FCO I14/SLICE_19
ROUTE         1     0.000      R5C7D.FCO to R5C8A.FCI      I14/un1_QEI_reg_cry_14
FCITOF0_DE  ---     1.181      R5C8A.FCI to       R5C8A.F0 I14/SLICE_18
ROUTE         1     0.000       R5C8A.F0 to R5C8A.DI0      I14/bus_in_15 (to clk_inferred_clock)
                  --------
                   18.254   (43.5% logic, 56.5% route), 11 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I14/SLICE_25:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R5C6B.CLK      clk_inferred_clock
                  --------
                    7.878   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I14/SLICE_18:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     7.878        OSC.OSC to R5C8A.CLK      clk_inferred_clock
                  --------
                    7.878   (0.0% logic, 100.0% route), 0 logic levels.

Report:   45.891MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "clk_inferred_clock"      |             |             |
38.000000 MHz ;                         |   38.000 MHz|   45.891 MHz|   2  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 7 clocks:

Clock Domain: clk_inferred_clock   Source: OSCInst0.OSC   Loads: 159
   Covered under: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;

   Data transfers from:
   Clock Domain: I16/wb_dat_o_0_sqmuxa   Source: I16/SLICE_289.F0
      Covered under: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;   Transfers: 2

   Clock Domain: I16_state_reg_3   Source: SLICE_143.F1
      Covered under: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;   Transfers: 11

   Clock Domain: I17/state_reg_derived_clock_2   Source: SLICE_102.Q0
      Covered under: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;   Transfers: 8

Clock Domain: I16/wb_dat_o_0_sqmuxa   Source: I16/SLICE_289.F0   Loads: 5
   No transfer within this clock domain is found

Clock Domain: I16_state_reg_3   Source: SLICE_143.F1   Loads: 11
   No transfer within this clock domain is found

Clock Domain: I15/spi_clk_o   Source: I15/EFBInst_0.SPISCKO   Loads: 1
   No transfer within this clock domain is found

Clock Domain: I15/spi_clk_i   Source: spi_clk.PAD   Loads: 1
   No transfer within this clock domain is found

Clock Domain: I17/state_reg_derived_clock_5   Source: SLICE_145.Q0   Loads: 4
   No transfer within this clock domain is found

Clock Domain: I17/state_reg_derived_clock_2   Source: SLICE_102.Q0   Loads: 5
   No transfer within this clock domain is found


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 5178 paths, 1 nets, and 1652 connections (80.2% coverage)