PAR: Place And Route Diamond_1.4_Production (87).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jun 15 12:38:58 2012

C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f
SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.p2t
SPI_Peripheral_Expansion_SPI_Peripheral_Expansion_map.ncd
SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.dir
SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.prf

Preference file: SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.prf.

Cost Table Summary
Level/      Number      Timing      Run         NCD
Cost [ncd]  Unrouted    Score       Time        Status
----------  --------    --------    -----       ------------
5_1   *     0           0           12          Complete        


* : Design saved.

par done!

Lattice Place and Route Report for Design "SPI_Peripheral_Expansion_SPI_Peripheral_Expansion_map.ncd"
Fri Jun 15 12:38:58 2012


Best Par Run
PAR: Place And Route Diamond_1.4_Production (87).
Command Line: C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f
SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.p2t
SPI_Peripheral_Expansion_SPI_Peripheral_Expansion_map.ncd
SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.dir
SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.prf
Preference file: SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file SPI_Peripheral_Expansion_SPI_Peripheral_Expansion_map.ncd.
Design name: Peripheral_Expansion_Top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-1200ZE
Package:     TQFP144
Performance: 1
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final          Version 22.4
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)      41/108          37% used
                     41/108          37% bonded
   IOLOGIC           10/108           9% used

   SLICE            260/640          40% used

   GSR                1/1           100% used
   OSC                1/1           100% used
   EFB                1/1           100% used


Number of Signals: 907
Number of Connections: 2061
WARNING - par: The SN pin is not available for use as a general purpose I/O pin when the SLAVE_SPI_PORT attribute is enabled.  The SN pin should be tied high with an external pull-up if you are not using the Slave SPI port for configuration.

Pin Constraint Summary:
   41 out of 41 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:
    clk_inferred_clock (driver: OSCInst0, clk load #: 159)


The following 3 signals are selected to use the secondary clock routing resources:
    nreset_c (driver: nreset, clk load #: 0, sr load #: 27, ce load #: 0)
    I16_state_reg_3 (driver: SLICE_143, clk load #: 6, sr load #: 0, ce load #: 1)
    I16/wb_dat_o_0_sqmuxa (driver: I16/SLICE_289, clk load #: 5, sr load #: 0, ce load #: 0)

WARNING - par: Signal "nreset_c" is selected to use Secondary clock resources; however its driver comp "nreset" is located at "140", which is not a dedicated pin for connecting to Secondary clock resources.  General routing has to be used to route this signal, and it may suffer from excessive delay or skew.
Signal nreset_c is selected as Global Set/Reset.
Starting Placer Phase 0.
..........
Finished Placer Phase 0.  REAL time: 0 secs 

Starting Placer Phase 1.
...................
Placer score = 83421.
Finished Placer Phase 1.  REAL time: 9 secs 

Starting Placer Phase 2.
.
Placer score =  82938
Finished Placer Phase 2.  REAL time: 9 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  General PIO: 1 out of 108 (0%)
  PLL        : 0 out of 1 (0%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "clk_inferred_clock" from OSC on comp "OSCInst0" on site "OSC", clk load = 159
  SECONDARY "nreset_c" from comp "nreset" on PIO site "140 (PT9D)", clk load = 0, ce load = 0, sr load = 27
  SECONDARY "I16/wb_dat_o_0_sqmuxa" from F0 on comp "I16/SLICE_289" on site "R7C12B", clk load = 5, ce load = 0, sr load = 0
  SECONDARY "I16_state_reg_3" from F1 on comp "SLICE_143" on site "R7C12C", clk load = 6, ce load = 1, sr load = 0

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 3 out of 8 (37%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   41 out of 108 (38.0%) PIO sites used.
   41 out of 108 (38.0%) bonded PIO sites used.
   Number of PIO comps: 41; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 10 / 28 ( 35%) | 2.5V       | -         |
| 1        | 18 / 26 ( 69%) | 2.5V       | -         |
| 2        | 11 / 28 ( 39%) | 2.5V       | -         |
| 3        | 2 / 26 (  7%)  | 2.5V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 9 secs 

Dumping design to file SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.dir/5_1.ncd.

0 connections routed; 2061 unrouted.
Starting router resource preassignment

WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
   Signal=I17/state_reg_derived_clock_5 loads=4 clock_loads=1
   Signal=I17/state_reg_derived_clock_2 loads=5 clock_loads=4

Completed router resource preassignment. Real time: 10 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
2061 successful; 0 unrouted; (0) real time: 11 secs 
Dumping design to file SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.dir/5_1.ncd.
Total CPU time 10 secs 
Total REAL time: 11 secs 
Completely routed.
End of route.  2061 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Timing score: 0 

Total REAL time to completion: 12 secs 

Dumping design to file SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.dir/5_1.ncd.


All signals are completely routed.


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.