Lattice Mapping Report File for Design Module 'Peripheral_Expansion_Top'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-1200ZE -t TQFP144 -s 1 -oc Commercial
     SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.ngd -o
     SPI_Peripheral_Expansion_SPI_Peripheral_Expansion_map.ncd -pr
     SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.prf -mp
     SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.mrp
     C:/Lattice_Proj/SPI_Peripheral_Expansion.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200ZETQFP144
Target Performance:   1
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  06/15/12  12:38:57


Design Summary
   Number of registers:    287
      PFU registers:    277
      PIO registers:    10
   Number of SLICEs:           260 out of   640 (41%)
      SLICEs(logic/ROM):       160 out of   160 (100%)
      SLICEs(logic/ROM/RAM):   100 out of   480 (21%)
          As RAM:            0 out of   480 (0%)
          As Logic/ROM:    100 out of   480 (21%)
   Number of logic LUT4s:     293
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:    108 (216 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     509
   Number of PIO sites used: 41 out of 108 (38%)
   Number of block RAMs:  0 out of 7 (0%)
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       Yes
   JTAG used :      No
   Readback used :  No
   Oscillator used :  Yes
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 1 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  16
     Net a_in_c: 1 loads, 1 rising, 0 falling (Driver: PIO a_in )

     Net clk_inferred_clock: 159 loads, 159 rising, 0 falling (Driver: OSCInst0
     )
     Net I16/wb_dat_o_0_sqmuxa: 5 loads, 5 rising, 0 falling (Driver:
     I16/wb_dat_o_0_sqmuxa )
     Net I16_state_reg_3: 6 loads, 0 rising, 6 falling (Driver:
     I16/state_reg_s0_0_a2 )
     Net I15/spi_clk_i: 1 loads, 1 rising, 0 falling (Driver: PIO spi_clk )
     Net I17/state_reg_derived_clock_5: 1 loads, 0 rising, 1 falling (Driver:
     I17/state_reg_5 )
     Net I17/state_reg_derived_clock_2: 4 loads, 4 rising, 0 falling (Driver:
     I17/state_reg_2 )
     Net tct_sw_c_7: 1 loads, 1 rising, 0 falling (Driver: PIO tct_sw_7 )
     Net tct_sw_c_6: 1 loads, 1 rising, 0 falling (Driver: PIO tct_sw_6 )
     Net tct_sw_c_5: 1 loads, 1 rising, 0 falling (Driver: PIO tct_sw_5 )
     Net tct_sw_c_4: 1 loads, 1 rising, 0 falling (Driver: PIO tct_sw_4 )
     Net tct_sw_c_3: 1 loads, 1 rising, 0 falling (Driver: PIO tct_sw_3 )
     Net tct_sw_c_2: 1 loads, 1 rising, 0 falling (Driver: PIO tct_sw_2 )
     Net tct_sw_c_1: 1 loads, 1 rising, 0 falling (Driver: PIO tct_sw_1 )
     Net tct_sw_c_0: 1 loads, 1 rising, 0 falling (Driver: PIO tct_sw_0 )
     Net b_in_c: 1 loads, 1 rising, 0 falling (Driver: PIO b_in )
   Number of Clock Enables:  22
     Net I13/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I13/q_reg_16: 1 loads, 1 LSLICEs
     Net I12/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I12/q_reg_16: 1 loads, 1 LSLICEs
     Net I16_state_reg_3: 1 loads, 1 LSLICEs
     Net I17/un44_reg_address_ff_0_i: 2 loads, 2 LSLICEs
     Net I25/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I25/q_reg_16: 1 loads, 1 LSLICEs
     Net I24/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I24/q_reg_16: 1 loads, 1 LSLICEs
     Net I23/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I23/q_reg_16: 1 loads, 1 LSLICEs
     Net I22/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I22/q_reg_16: 1 loads, 1 LSLICEs
     Net I21/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I21/q_reg_16: 1 loads, 1 LSLICEs
     Net I20/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I20/q_reg_16: 1 loads, 1 LSLICEs
     Net I19/q_rege_0_i: 9 loads, 9 LSLICEs
     Net I19/q_reg_16: 1 loads, 1 LSLICEs
     Net I18/q_reg_16: 1 loads, 1 LSLICEs
     Net I18/q_rege_0_i: 9 loads, 9 LSLICEs
   Number of local set/reset loads for net nreset_c merged into GSR:  34
   Number of LSRs:  4
     Net nreset_c: 27 loads, 17 LSLICEs
     Net I14/a_in_dff: 1 loads, 1 LSLICEs
     Net wb_rst_i: 1 loads, 0 LSLICEs
     Net I17/fb: 1 loads, 1 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net nreset_c: 209 loads
     Net I2_q_reg_16: 26 loads
     Net I2_q_reg_15: 22 loads
     Net reg_address_o_0: 21 loads
     Net I12/DFF2: 19 loads

     Net I12_DFF1: 19 loads
     Net I13/DFF2: 19 loads
     Net I13_DFF1: 19 loads
     Net I25/DFF2: 19 loads
     Net I25_DFF1: 19 loads




   Number of warnings:  1
   Number of errors:    0




Design Errors/Warnings

WARNING: Using local reset signal 'nreset_c' to infer global GSR net.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| LED_out_4           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| busy_out            | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| Gray_in_0           | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| spi_clk             | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| spi_mosi            | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| spi_miso            | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| spi_irq             | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED_out_7           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED_out_6           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED_out_5           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED_out_3           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED_out_2           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED_out_1           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED_out_0           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| sseg_7              | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| sseg_6              | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+

| sseg_5              | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| sseg_4              | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| sseg_3              | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| sseg_2              | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| sseg_1              | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| sseg_0              | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| an_3                | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| an_2                | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| an_1                | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| an_0                | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| tct_sw_7            | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| tct_sw_6            | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| tct_sw_5            | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| tct_sw_4            | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| tct_sw_3            | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| tct_sw_2            | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| tct_sw_1            | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| tct_sw_0            | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| b_in                | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| a_in                | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| spi_scsn            | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| nreset              | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| Gray_in_3           | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| Gray_in_2           | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| Gray_in_1           | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Signal I17/GN was merged into signal I17/state_reg_derived_clock_5
Signal SEDSTDBY undriven or does not drive anything - clipped.

Signal I18/q_reg_cry_0_COUT_15 undriven or does not drive anything - clipped.
Signal I18/q_reg_cry_0_S0_0 undriven or does not drive anything - clipped.
Signal I19/q_reg_cry_0_S0_0_0 undriven or does not drive anything - clipped.
Signal I19/q_reg_cry_0_COUT_0_15 undriven or does not drive anything - clipped.
Signal I20/q_reg_cry_0_S0_1_0 undriven or does not drive anything - clipped.
Signal I20/q_reg_cry_0_COUT_1_15 undriven or does not drive anything - clipped.
Signal I21/q_reg_cry_0_S0_2_0 undriven or does not drive anything - clipped.
Signal I21/q_reg_cry_0_COUT_2_15 undriven or does not drive anything - clipped.
Signal I22/q_reg_cry_0_S0_3_0 undriven or does not drive anything - clipped.
Signal I22/q_reg_cry_0_COUT_3_15 undriven or does not drive anything - clipped.
Signal I23/q_reg_cry_0_S0_4_0 undriven or does not drive anything - clipped.
Signal I23/q_reg_cry_0_COUT_4_15 undriven or does not drive anything - clipped.
Signal I24/q_reg_cry_0_S0_5_0 undriven or does not drive anything - clipped.
Signal I24/q_reg_cry_0_COUT_5_15 undriven or does not drive anything - clipped.
Signal I25/q_reg_cry_0_S0_6_0 undriven or does not drive anything - clipped.
Signal I25/q_reg_cry_0_COUT_6_15 undriven or does not drive anything - clipped.
Signal I15/CFGSTDBY undriven or does not drive anything - clipped.
Signal I15/CFGWAKE undriven or does not drive anything - clipped.
Signal I15/WBCUFMIRQ undriven or does not drive anything - clipped.
Signal I15/TCOC undriven or does not drive anything - clipped.
Signal I15/TCINT undriven or does not drive anything - clipped.
Signal I15/SPICSNEN undriven or does not drive anything - clipped.
Signal I15/SPIMCSN7 undriven or does not drive anything - clipped.
Signal I15/SPIMCSN6 undriven or does not drive anything - clipped.
Signal I15/SPIMCSN5 undriven or does not drive anything - clipped.
Signal I15/SPIMCSN4 undriven or does not drive anything - clipped.
Signal I15/SPIMCSN3 undriven or does not drive anything - clipped.
Signal I15/SPIMCSN2 undriven or does not drive anything - clipped.
Signal I15/SPIMCSN1 undriven or does not drive anything - clipped.
Signal I15/SPIMCSN0 undriven or does not drive anything - clipped.
Signal I15/I2C2IRQO undriven or does not drive anything - clipped.
Signal I15/I2C1IRQO undriven or does not drive anything - clipped.
Signal I15/I2C2SDAOEN undriven or does not drive anything - clipped.
Signal I15/I2C2SDAO undriven or does not drive anything - clipped.
Signal I15/I2C2SCLOEN undriven or does not drive anything - clipped.
Signal I15/I2C2SCLO undriven or does not drive anything - clipped.
Signal I15/I2C1SDAOEN undriven or does not drive anything - clipped.
Signal I15/I2C1SDAO undriven or does not drive anything - clipped.
Signal I15/I2C1SCLOEN undriven or does not drive anything - clipped.
Signal I15/I2C1SCLO undriven or does not drive anything - clipped.
Signal I15/PLLDATO0 undriven or does not drive anything - clipped.
Signal I15/PLLDATO1 undriven or does not drive anything - clipped.
Signal I15/PLLDATO2 undriven or does not drive anything - clipped.
Signal I15/PLLDATO3 undriven or does not drive anything - clipped.
Signal I15/PLLDATO4 undriven or does not drive anything - clipped.
Signal I15/PLLDATO5 undriven or does not drive anything - clipped.
Signal I15/PLLDATO6 undriven or does not drive anything - clipped.
Signal I15/PLLDATO7 undriven or does not drive anything - clipped.
Signal I15/PLLADRO0 undriven or does not drive anything - clipped.
Signal I15/PLLADRO1 undriven or does not drive anything - clipped.
Signal I15/PLLADRO2 undriven or does not drive anything - clipped.
Signal I15/PLLADRO3 undriven or does not drive anything - clipped.
Signal I15/PLLADRO4 undriven or does not drive anything - clipped.
Signal I15/PLLWEO undriven or does not drive anything - clipped.
Signal I15/PLL1STBO undriven or does not drive anything - clipped.
Signal I15/PLL0STBO undriven or does not drive anything - clipped.

Signal I15/PLLRSTO undriven or does not drive anything - clipped.
Signal I15/PLLCLKO undriven or does not drive anything - clipped.
Signal I2/q_reg_cry_0_S0_9_0 undriven or does not drive anything - clipped.
Signal I2/q_reg_cry_0_COUT_9_15 undriven or does not drive anything - clipped.
Signal I14/un1_QEI_reg_cry_0_0_S1 undriven or does not drive anything - clipped.
Signal I14/un1_QEI_reg_cry_0_0_S0 undriven or does not drive anything - clipped.
Signal I14/un1_QEI_reg_s_15_0_S1 undriven or does not drive anything - clipped.
Signal I14/un1_QEI_reg_s_15_0_COUT undriven or does not drive anything -
     clipped.
Signal I12/q_reg_cry_0_S0_7_0 undriven or does not drive anything - clipped.
Signal I12/q_reg_cry_0_COUT_7_15 undriven or does not drive anything - clipped.
Signal I13/q_reg_cry_0_S0_8_0 undriven or does not drive anything - clipped.
Signal I13/q_reg_cry_0_COUT_8_15 undriven or does not drive anything - clipped.
Block I17/w_enable_GN was optimized away.



Memory Usage


OSC Summary
-----------

OSC 1:                                     Pin/Node Value
  OSC Instance Name:                                OSCInst0
  OSC Type:                                         OSCH
  STDBY Input:                                      NONE
  OSC Output:                              NODE     clk_inferred_clock
  OSC Nominal Frequency (MHz):                      38.00

Embedded Functional Block Connection Summary:
---------------------------------------------

   Desired WISHBONE clock frequency: 38.0 MHz
   Clock source:                     clk_inferred_clock
   Reset source:                     wb_rst_i
   Functions mode:
      I2C #1 (Primary) Function:     DISABLED
      I2C #2 (Secondary) Function:   DISABLED
      SPI Function:                  ENABLED
      Timer/Counter Function:        DISABLED
      Timer/Counter Mode:            WB
      UFM Connection:                DISABLED
      PLL0 Connection:               DISABLED
      PLL1 Connection:               DISABLED
   I2C Function Summary:
   --------------------
      None
   SPI Function Summary:
   --------------------
      SPI Mode:               SLAVE
      SPI Data Order:         MSB to LSB
      SPI Clock Inversion:    DISABLED
      SPI Phase Adjust:       DISABLED
      SPI Wakeup:             DISABLED
   Timer/Counter Function Summary:

   ------------------------------
      None
   UFM Function Summary:
   --------------------
      UFM Utilization:        General Purpose Flash Memory
      Available General
      Purpose Flash Memory:   511 Pages (511*128 Bits)

      EBR Blocks with Unique
      Initialization Data:    0

      WID		EBR Instance
      ---		------------



ASIC Components
---------------

Instance Name: I15/EFBInst_0
         Type: EFB
Instance Name: OSCInst0
         Type: OSCH



GSR Usage
---------

GSR Component:
   The local reset signal 'nreset_c' of the design has been inferred as Global
        Set Reset (GSR). The reset signal used for GSR control is 'nreset_c'.

GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.

Components on inferred reset domain with GSR Property disabled
--------------------------------------------------------------

These components have the GSR property set to DISABLED and are on the inferred
     reset domain. The components will respond to the reset signal 'nreset_c'
     via the local reset on the component and not the GSR component.

Type and number of components of the type:
   Register = 31

Type and instance name of component:
   Register : I12_DFF1io
   Register : I13/DFF2
   Register : I12/DFF2
   Register : I16/state_reg_0
   Register : I16/state_reg_1
   Register : I17/reg_address_o_1_3
   Register : I17/state_reg_0
   Register : I17/state_reg_1
   Register : I17/state_reg_2
   Register : I17/state_reg_3
   Register : I17/state_reg_4
   Register : I17/reg_address_o_1_0
   Register : I17/reg_address_o_1_1
   Register : I17/reg_address_o_1_2
   Register : I25/DFF2
   Register : I24/DFF2
   Register : I23/DFF2

   Register : I22/DFF2
   Register : I21/DFF2
   Register : I20/DFF2
   Register : I19/DFF2
   Register : I18/DFF2
   Register : I25_DFF1io
   Register : I24_DFF1io
   Register : I23_DFF1io
   Register : I22_DFF1io
   Register : I21_DFF1io
   Register : I20_DFF1io
   Register : I19_DFF1io
   Register : I18_DFF1io
   Register : I13_DFF1io



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs
   Total REAL Time: 0 secs
   Peak Memory Usage: 34 MB






































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