I/O Timing Report
// Design: Peripheral_Expansion_Top
// Package: TQFP144
// ncd File: spi_peripheral_expansion_spi_peripheral_expansion.ncd
// Version: Diamond_1.4_Production (87)
// Written on Fri Jun 15 12:39:12 2012
// M: Minimum Performance Grade
// iotiming SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.ncd SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.prf

I/O Timing Report (All units are in ns)

Worst Case Results across Performance Grades (M, 3, 2, 1):

// Input Setup and Hold Times

Port     Clock   Edge  Setup Performance_Grade  Hold Performance_Grade
----------------------------------------------------------------------
spi_scsn spi_clk R    11.700      1      -1.928     M


// Clock to Output Delay

Port     Clock   Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
------------------------------------------------------------------------
spi_miso spi_clk R    12.961         1        2.001          M
spi_mosi spi_clk R    12.693         1        2.735          M


// Internal_Clock to Input

Port     Internal_Clock    
--------------------------------------------------------
Gray_in_ I16_state_reg_3   
Gray_in_ I16_state_reg_3   
Gray_in_ I16_state_reg_3   
Gray_in_ I16_state_reg_3   
a_in     clk_inferred_clock
b_in     clk_inferred_clock
nreset   clk_inferred_clock
spi_miso I15/spi_clk_o     
spi_mosi I15/spi_clk_o     
tct_sw_0 clk_inferred_clock
tct_sw_1 clk_inferred_clock
tct_sw_2 clk_inferred_clock
tct_sw_3 clk_inferred_clock
tct_sw_4 clk_inferred_clock
tct_sw_5 clk_inferred_clock
tct_sw_6 clk_inferred_clock
tct_sw_7 clk_inferred_clock


// Internal_Clock to Output

Port     Internal_Clock    
--------------------------------------------------------
an_0     clk_inferred_clock
an_1     clk_inferred_clock
an_2     clk_inferred_clock
an_3     clk_inferred_clock
busy_out clk_inferred_clock
spi_clk  I15/spi_clk_o     
spi_irq  clk_inferred_clock
spi_miso I15/spi_clk_o     
spi_mosi I15/spi_clk_o     
sseg_0   clk_inferred_clock
sseg_1   clk_inferred_clock
sseg_2   clk_inferred_clock
sseg_3   clk_inferred_clock
sseg_4   clk_inferred_clock
sseg_5   clk_inferred_clock
sseg_6   clk_inferred_clock