Synthesis and Ngdbuild Report #Build: Synplify Pro F-2011.09L, Build 022R, Oct 19 2011 #install: C:\lscc\diamond\1.4\synpbase #OS: Windows XP 5.1 #Hostname: LT11878 $ Start of Compile #Fri Jun 15 12:38:48 2012 Synopsys VHDL Compiler, version comp560rcp1, Build 045R, built Oct 18 2011 @N|Running in 32-bit mode Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @N: CD720 :"C:\lscc\diamond\1.4\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\Peripheral_Expansion_Top.vhd":31:7:31:30|Top entity is set to Peripheral_Expansion_Top. VHDL syntax check successful! Options changed - recompiling @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\Peripheral_Expansion_Top.vhd":31:7:31:30|Synthesizing work.peripheral_expansion_top.arch @N: CD630 :"C:\lscc\diamond\1.4\cae_library\synthesis\vhdl\machxo2.vhd":2289:10:2289:13|Synthesizing work.osch.syn_black_box Post processing for work.osch.syn_black_box @W: CD638 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\Peripheral_Expansion_Top.vhd":54:10:54:12|Signal gnd is undriven @W: CD638 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\Peripheral_Expansion_Top.vhd":55:10:55:12|Signal vcc is undriven @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\dbounce.vhd":30:7:30:13|Synthesizing work.dbounce.arch Post processing for work.dbounce.arch @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\QEI_int.vhd":33:7:33:9|Synthesizing work.qei.arch Post processing for work.qei.arch @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\hex_to_sseg.vhd":27:7:27:17|Synthesizing work.hex_to_sseg.arch Post processing for work.hex_to_sseg.arch @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\disp_mux.vhd":29:7:29:14|Synthesizing work.disp_mux.arch Post processing for work.disp_mux.arch @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\GrayDecoder.vhd":28:7:28:17|Synthesizing work.graydecoder.arch Post processing for work.graydecoder.arch @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_wbController.vhd":45:7:45:22|Synthesizing work.spi_wbcontroller.arch @N: CD233 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_wbController.vhd":70:17:70:18|Using sequential encoding for type state_type Post processing for work.spi_wbcontroller.arch @W: CL117 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_wbController.vhd":108:3:108:6|Latch generated from process for signal wb_dat_i(7 downto 0); possible missing assignment in an if or case statement. @W: CL117 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_wbController.vhd":108:3:108:6|Latch generated from process for signal wb_we_i; possible missing assignment in an if or case statement. @W: CL117 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_wbController.vhd":108:3:108:6|Latch generated from process for signal wb_dat_o(7 downto 0); possible missing assignment in an if or case statement. @W: CL117 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_wbController.vhd":108:3:108:6|Latch generated from process for signal wb_adr_i(7 downto 0); possible missing assignment in an if or case statement. @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Bus.vhd":14:7:14:13|Synthesizing work.spi_bus.structure @N: CD630 :"C:\lscc\diamond\1.4\cae_library\synthesis\vhdl\machxo2.vhd":2300:10:2300:12|Synthesizing work.efb.syn_black_box Post processing for work.efb.syn_black_box @N: CD630 :"C:\lscc\diamond\1.4\cae_library\synthesis\vhdl\machxo2.vhd":1488:10:1488:12|Synthesizing work.vlo.syn_black_box Post processing for work.vlo.syn_black_box @N: CD630 :"C:\lscc\diamond\1.4\cae_library\synthesis\vhdl\machxo2.vhd":105:10:105:11|Synthesizing work.bb.syn_black_box Post processing for work.bb.syn_black_box @N: CD630 :"C:\lscc\diamond\1.4\cae_library\synthesis\vhdl\machxo2.vhd":1481:10:1481:12|Synthesizing work.vhi.syn_black_box Post processing for work.vhi.syn_black_box Post processing for work.spi_bus.structure @N: CD630 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":40:7:40:18|Synthesizing work.spi_data_mux.arch @N: CD231 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":66:17:66:18|Using onehot encoding for type state_type (ready="100000") Post processing for work.spi_data_mux.arch @W: CL117 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":102:3:102:6|Latch generated from process for signal reg_address_ff(7 downto 0); possible missing assignment in an if or case statement. @W: CL117 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":102:3:102:6|Latch generated from process for signal w_enable; possible missing assignment in an if or case statement. @W: CL189 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":232:3:232:4|Register bit reg_address_o(4) is always 0, optimizing ... @W: CL189 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":232:3:232:4|Register bit reg_address_o(5) is always 0, optimizing ... @W: CL189 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":232:3:232:4|Register bit reg_address_o(6) is always 0, optimizing ... @W: CL189 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":232:3:232:4|Register bit reg_address_o(7) is always 0, optimizing ... @W: CL279 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":232:3:232:4|Pruning register bits 7 to 4 of reg_address_o(7 downto 0) Post processing for work.peripheral_expansion_top.arch @N: CL201 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":80:3:80:4|Trying to extract state machine for register state_reg Extracted state machine for register state_reg State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @W: CL159 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":47:4:47:8|Input QEI_1 is unused @W: CL159 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":48:4:48:8|Input QEI_2 is unused @W: CL159 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":49:4:49:8|Input QEI_3 is unused @W: CL159 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":50:4:50:8|Input QEI_4 is unused @W: CL159 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_Data_MUX.vhd":52:4:52:14|Input Gray_code_1 is unused @N: CL201 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\SPI_wbController.vhd":82:3:82:4|Trying to extract state machine for register state_reg Extracted state machine for register state_reg State machine has 4 reachable states with original encodings of: 00 01 10 11 @W: CL157 :"C:\Lattice_Proj\SPI_Peripheral_Expansion\source\Peripheral_Expansion_Top.vhd":320:13:320:25|Output LED_out has undriven bits -- simulation mismatch possible. @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Jun 15 12:38:48 2012 ###########################################################] Premap Report (contents appended below) @N:"C:\Lattice_Proj\SPI_Peripheral_Expansion\synlog\SPI_Peripheral_Expansion_SPI_Peripheral_Expansion_premap.srr" Synopsys Lattice Technology Pre-mapping, Version maplat, Build 239R, Built Oct 19 2011 10:56:21 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version F-2011.09L Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB) @W: MT462 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":133:8:133:21|Net I16.wb_dat_i_1_sqmuxa appears to be an unidentified clock source. Assuming default frequency. @W: MT462 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":172:4:172:17|Net I16.wb_dat_o_0_sqmuxa appears to be an unidentified clock source. Assuming default frequency. syn_allowed_resources : blockrams=7 set on top level netlist Peripheral_Expansion_Top Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 77MB) Pre Mapping successful! At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Jun 15 12:38:50 2012 ###########################################################] Map & Optimize Report (contents appended below) @N:"C:\Lattice_Proj\SPI_Peripheral_Expansion\synlog\SPI_Peripheral_Expansion_SPI_Peripheral_Expansion_fpga_mapper.srr" Synopsys Lattice Technology Mapper, Version maplat, Build 239R, Built Oct 19 2011 10:56:21 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version F-2011.09L Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF203 |Set autoconstraint_io Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 77MB) @W: MO111 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":320:13:320:25|Tristate driver LED_out_1 on net LED_out_1 has its enable tied to GND (module Peripheral_Expansion_Top) @W: MO111 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":320:13:320:25|Tristate driver LED_out_2 on net LED_out_2 has its enable tied to GND (module Peripheral_Expansion_Top) @W: MO111 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":320:13:320:25|Tristate driver LED_out_3 on net LED_out_3 has its enable tied to GND (module Peripheral_Expansion_Top) @W: MO111 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":320:13:320:25|Tristate driver LED_out_4 on net LED_out_4 has its enable tied to GND (module Peripheral_Expansion_Top) Available hyper_sources - for debug and ip models None Found @W: MT462 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":172:4:172:17|Net I16.wb_dat_o_0_sqmuxa appears to be an unidentified clock source. Assuming default frequency. @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Rom I6.sseg_1[6:0] mapped in logic. @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Rom I5.sseg_1[6:0] mapped in logic. @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Rom I4.sseg_1[6:0] mapped in logic. @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Rom I3.sseg_1[6:0] mapped in logic. @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\graydecoder.vhd":59:3:59:8|Rom I1.Decode_out_1[3:0] mapped in logic. @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Rom I6.sseg_1[6:0] mapped in logic. @N: MO106 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Found ROM, 'I6.sseg_1[6:0]', 15 words by 7 bits @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Rom I5.sseg_1[6:0] mapped in logic. @N: MO106 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Found ROM, 'I5.sseg_1[6:0]', 15 words by 7 bits @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Rom I4.sseg_1[6:0] mapped in logic. @N: MO106 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Found ROM, 'I4.sseg_1[6:0]', 15 words by 7 bits @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Rom I3.sseg_1[6:0] mapped in logic. @N: MO106 :"c:\lattice_proj\spi_peripheral_expansion\source\hex_to_sseg.vhd":53:3:53:11|Found ROM, 'I3.sseg_1[6:0]', 1 words by 7 bits @N: FA239 :"c:\lattice_proj\spi_peripheral_expansion\source\graydecoder.vhd":59:3:59:8|Rom I1.Decode_out_1[3:0] mapped in logic. @N: MO106 :"c:\lattice_proj\spi_peripheral_expansion\source\graydecoder.vhd":59:3:59:8|Found ROM, 'I1.Decode_out_1[3:0]', 16 words by 4 bits Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 77MB) @N:"c:\lattice_proj\spi_peripheral_expansion\source\disp_mux.vhd":57:2:57:3|Found counter in view:work.Peripheral_Expansion_Top(arch) inst I2.q_reg[16:0] @N:"c:\lattice_proj\spi_peripheral_expansion\source\dbounce.vhd":61:8:61:9|Found counter in view:work.DBounce(arch) inst q_reg[16:0] Encoding state machine work.SPI_Data_MUX(arch)-state_reg[0:5] original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine work.SPI_wbController(arch)-state_reg[0:3] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:"c:\lattice_proj\spi_peripheral_expansion\source\dbounce.vhd":61:8:61:9|Found counter in view:work.DBounce_0(arch) inst q_reg[16:0] Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) @W: BN132 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":108:3:108:6|Removing instance I16.wb_adr_i[7], because it is equivalent to instance I16.wb_adr_i[5] @W: BN132 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":108:3:108:6|Removing instance I16.wb_adr_i[5], because it is equivalent to instance I16.wb_adr_i[2] @W: BN132 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":108:3:108:6|Removing instance I16.wb_adr_i[6], because it is equivalent to instance I16.wb_adr_i[4] @W: BN132 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":108:3:108:6|Removing instance I16.wb_adr_i[4], because it is equivalent to instance I16.wb_adr_i[3] #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== I14.a_in_rising_edge:C Not Done ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 77MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 77MB) Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 80MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -9.30ns 274 / 258 2 0h:00m:00s -8.89ns 277 / 258 3 0h:00m:00s -8.89ns 277 / 258 4 0h:00m:00s -8.89ns 277 / 258 ------------------------------------------------------------ @N: FX271 :"c:\lattice_proj\spi_peripheral_expansion\source\qei_int.vhd":69:2:69:3|Instance "I14.QEI_reg[0]" with 4 loads has been replicated 1 time(s) to improve timing Timing driven replication report Added 1 Registers via timing driven replication Added 0 LUTs via timing driven replication Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s -7.56ns 287 / 259 2 0h:00m:01s -7.56ns 287 / 259 3 0h:00m:02s -7.56ns 287 / 259 4 0h:00m:02s -7.56ns 287 / 259 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -7.56ns 287 / 259 2 0h:00m:02s -7.56ns 287 / 259 3 0h:00m:02s -7.56ns 287 / 259 4 0h:00m:02s -7.56ns 287 / 259 ------------------------------------------------------------ @N: FX104 |Net "nreset_c" with "181" loads has been buffered by "2" buffers due to a soft fanout limit of "100" Net buffering Report for view:work.Peripheral_Expansion_Top(arch): Added 2 Buffers Added 0 Registers via replication Added 0 LUTs via replication Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 77MB peak: 80MB) @N: FX164 |The option to pack flops in the IOB has not been specified @W: MO129 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":108:3:108:6|Sequential instance I16.wb_adr_i[3] reduced to a combinational gate by constant propagation @W: MO129 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_wbcontroller.vhd":108:3:108:6|Sequential instance I16.wb_adr_i[2] reduced to a combinational gate by constant propagation @W: MO111 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":44:4:44:10|Tristate driver LED_out_obuft_4_.un1[0] on net LED_out[4] has its enable tied to GND (module Peripheral_Expansion_Top) @W: MO111 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":44:4:44:10|Tristate driver LED_out_obuft_5_.un1[0] on net LED_out[5] has its enable tied to GND (module Peripheral_Expansion_Top) @W: MO111 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":44:4:44:10|Tristate driver LED_out_obuft_6_.un1[0] on net LED_out[6] has its enable tied to GND (module Peripheral_Expansion_Top) @W: MO111 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":44:4:44:10|Tristate driver LED_out_obuft_7_.un1[0] on net LED_out[7] has its enable tied to GND (module Peripheral_Expansion_Top) Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 78MB peak: 80MB) Writing Analyst data base C:\Lattice_Proj\SPI_Peripheral_Expansion\SPI_Peripheral_Expansion_SPI_Peripheral_Expansion.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current: 77MB peak: 80MB) Writing EDIF Netlist and constraint files F-2011.09L Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:03s; Memory used current: 81MB peak: 82MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 81MB peak: 82MB) ================= Gated clock report ================= The following instances have been converted Seq Inst Instance Port Clock -------------------------------------------------------- I16.wb_dat_i[7] CK I16.state_reg_i[3] I16.wb_dat_i[6] CK I16.state_reg_i[3] I16.wb_dat_i[5] CK I16.state_reg_i[3] I16.wb_dat_i[4] CK I16.state_reg_i[3] I16.wb_dat_i[3] CK I16.state_reg_i[3] I16.wb_dat_i[2] CK I16.state_reg_i[3] I16.wb_dat_i[1] CK I16.state_reg_i[3] I16.wb_dat_i[0] CK I16.state_reg_i[3] ======================================================== The following instances have NOT been converted Seq Inst Instance Port Clock Reason for not converting -------------------------------------------------------------------------------------------------------------------------------------------------- I16.wb_dat_o[7] CK I16.wb_dat_o_0_sqmuxa Gated clock does not have declared clock, add/enable clock constraint in SDC file. I16.wb_dat_o[6] CK I16.wb_dat_o_0_sqmuxa Gated clock does not have declared clock, add/enable clock constraint in SDC file. I16.wb_dat_o[5] CK I16.wb_dat_o_0_sqmuxa Gated clock does not have declared clock, add/enable clock constraint in SDC file. I16.wb_dat_o[4] CK I16.wb_dat_o_0_sqmuxa Gated clock does not have declared clock, add/enable clock constraint in SDC file. I16.wb_dat_o[3] CK I16.wb_dat_o_0_sqmuxa Gated clock does not have declared clock, add/enable clock constraint in SDC file. I16.wb_dat_o[2] CK I16.wb_dat_o_0_sqmuxa Gated clock does not have declared clock, add/enable clock constraint in SDC file. I16.wb_dat_o[1] CK I16.wb_dat_o_0_sqmuxa Gated clock does not have declared clock, add/enable clock constraint in SDC file. I16.wb_dat_o[0] CK I16.wb_dat_o_0_sqmuxa Gated clock does not have declared clock, add/enable clock constraint in SDC file. ================================================================================================================================================== ================= End gated clock report ================= Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 81MB peak: 82MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 81MB peak: 82MB) @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 81MB peak: 82MB) @W: MT246 :"c:\lattice_proj\spi_peripheral_expansion\source\peripheral_expansion_top.vhd":245:3:245:10|Blackbox OSCH is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\lattice_proj\spi_peripheral_expansion\source\spi_bus.vhd":164:4:164:12|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock Peripheral_Expansion_Top|clk_inferred_clock with period 5.00ns. Please declare a user-defined clock on object "n:clk" Found clock SPI_wbController|state_reg_derived_clock[3] with period 5.00ns Found clock SPI_Data_MUX|state_reg_derived_clock[2] with period 5.00ns Found clock SPI_Data_MUX|state_reg_derived_clock[5] with period 5.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Jun 15 12:38:54 2012 # Top view: Peripheral_Expansion_Top Requested Frequency: 200.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing. Performance Summary ******************* Worst slack in design: -8.356 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Peripheral_Expansion_Top|clk_inferred_clock 200.0 MHz 54.1 MHz 5.000 18.489 -6.744 inferred Inferred_clkgroup_0 SPI_Data_MUX|state_reg_derived_clock[2] 200.0 MHz 268.5 MHz 5.000 3.725 1.275 derived (from Peripheral_Expansion_Top|clk_inferred_clock) Inferred_clkgroup_0 SPI_Data_MUX|state_reg_derived_clock[5] 200.0 MHz 398.9 MHz 5.000 2.507 2.840 derived (from Peripheral_Expansion_Top|clk_inferred_clock) Inferred_clkgroup_0 SPI_wbController|state_reg_derived_clock[3] 200.0 MHz 54.1 MHz 5.000 18.489 3.028 derived (from Peripheral_Expansion_Top|clk_inferred_clock) Inferred_clkgroup_0 System 200.0 MHz 140.3 MHz 5.000 7.129 -2.129 system system_clkgroup ===================================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 5.000 -2.129 | No paths - | No paths - | No paths - System Peripheral_Expansion_Top|clk_inferred_clock | 5.000 0.645 | No paths - | No paths - | No paths - System SPI_wbController|state_reg_derived_clock[3] | No paths - | No paths - | 5.000 -1.206 | No paths - System SPI_Data_MUX|state_reg_derived_clock[2] | 5.000 3.787 | No paths - | No paths - | No paths - Peripheral_Expansion_Top|clk_inferred_clock System | 5.000 -8.356 | No paths - | No paths - | No paths - Peripheral_Expansion_Top|clk_inferred_clock Peripheral_Expansion_Top|clk_inferred_clock | 5.000 -1.981 | No paths - | No paths - | No paths - Peripheral_Expansion_Top|clk_inferred_clock SPI_wbController|state_reg_derived_clock[3] | No paths - | No paths - | 2.500 -6.744 | No paths - Peripheral_Expansion_Top|clk_inferred_clock SPI_Data_MUX|state_reg_derived_clock[5] | No paths - | No paths - | 2.500 1.247 | No paths - SPI_wbController|state_reg_derived_clock[3] System | No paths - | No paths - | No paths - | 5.000 3.956 SPI_wbController|state_reg_derived_clock[3] SPI_wbController|state_reg_derived_clock[3] | No paths - | 5.000 3.028 | No paths - | No paths - SPI_Data_MUX|state_reg_derived_clock[5] SPI_wbController|state_reg_derived_clock[3] | No paths - | 5.000 2.840 | No paths - | No paths - SPI_Data_MUX|state_reg_derived_clock[2] Peripheral_Expansion_Top|clk_inferred_clock | 5.000 1.275 | No paths - | No paths - | No paths - ================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock -------------------------------------------------------------------------------- Gray_in[0] System (rising) NA 0.000 -2.129 Gray_in[1] System (rising) NA 0.000 -2.097 Gray_in[2] System (rising) NA 0.000 -2.057 Gray_in[3] System (rising) NA 0.000 -1.953 a_in System (rising) NA 0.000 2.915 b_in System (rising) NA 0.000 2.915 nreset System (rising) NA 0.000 0.645 spi_clk System (rising) NA 0.000 3.588 spi_miso System (rising) NA 0.000 3.588 spi_mosi System (rising) NA 0.000 3.588 spi_scsn System (rising) NA 0.000 3.020 tct_sw[0] System (rising) NA 0.000 2.915 tct_sw[1] System (rising) NA 0.000 2.915 tct_sw[2] System (rising) NA 0.000 2.915 tct_sw[3] System (rising) NA 0.000 2.915 tct_sw[4] System (rising) NA 0.000 2.915 tct_sw[5] System (rising) NA 0.000 2.915 tct_sw[6] System (rising) NA 0.000 2.915 tct_sw[7] System (rising) NA 0.000 2.915 ================================================================================ Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock --------------------------------------------------------------------------------------------------------------------- LED_out[0] System (rising) NA 7.129 5.000 LED_out[1] System (rising) NA 7.129 5.000 LED_out[2] System (rising) NA 7.129 5.000 LED_out[3] System (rising) NA 6.680 5.000 LED_out[4] NA NA NA NA NA LED_out[5] NA NA NA NA NA LED_out[6] NA NA NA NA NA LED_out[7] NA NA NA NA NA an[0] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 6.203 5.000 an[1] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 6.203 5.000 an[2] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 6.203 5.000 an[3] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 6.203 5.000 busy_out NA NA NA NA NA spi_clk System (rising) NA 4.011 5.000 spi_irq System (rising) NA 3.884 5.000 spi_miso System (rising) NA 4.011 5.000 spi_mosi System (rising) NA 4.011 5.000 sseg[0] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 12.486 5.000 sseg[1] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 12.486 5.000 sseg[2] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 13.356 5.000 sseg[3] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 12.486 5.000 sseg[4] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 12.486 5.000 sseg[5] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 13.352 5.000 sseg[6] Peripheral_Expansion_Top|clk_inferred_clock (rising) NA 12.486 5.000 sseg[7] NA NA NA NA NA ===================================================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lcmxo2_1200ze-1 Register bits: 259 of 1280 (20%) Latch bits: 28 PIC Latch: 0 I/O cells: 41 Details: BB: 3 CCU2D: 108 FD1P3AX: 180 FD1P3IX: 5 FD1S1AY: 28 FD1S3AX: 12 FD1S3DX: 34 FD1S3IX: 17 FD1S3JX: 1 GSR: 1 IB: 16 IFS1P3IX: 10 INV: 15 OB: 18 OBZ: 4 ORCALUT4: 277 PFUMX: 7 PUR: 1 VHI: 1 VLO: 1 false: 20 true: 20 Mapper successful! At Mapper Exit (Time elapsed 0h:00m:03s; Memory used current: 26MB peak: 82MB) Process took 0h:00m:04s realtime, 0h:00m:03s cputime # Fri Jun 15 12:38:54 2012 ###########################################################]