--------------------------------------------------------------------------------
Lattice TRACE Report - Hold
Fri Jun 15 12:25:52 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design file:     Peripheral_Expansion_Top
Device,speed:    LCMXO2-1200ZE,M
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;
            30 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 

Passed: The following path meets requirements by 0.688ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I23/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I23/DB_out  (to clk_inferred_clock +)

   Delay:               0.621ns  (41.4% logic, 58.6% route), 1 logic levels.

 Constraint Details:

      0.621ns physical path delay I23/SLICE_61 to I23/SLICE_62 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.688ns

 Physical Path Details:

      Data path I23/SLICE_61 to I23/SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257     R8C13B.CLK to      R8C13B.Q0 I23/SLICE_61 (from clk_inferred_clock)
ROUTE        19     0.364      R8C13B.Q0 to R8C13A.M0      I23/DFF2 (to clk_inferred_clock)
                  --------
                    0.621   (41.4% logic, 58.6% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I23/SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R8C13B.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I23/SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R8C13A.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.688ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I12/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I12/DB_out  (to clk_inferred_clock +)

   Delay:               0.621ns  (41.4% logic, 58.6% route), 1 logic levels.

 Constraint Details:

      0.621ns physical path delay I12/SLICE_16 to I12/SLICE_17 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.688ns

 Physical Path Details:

      Data path I12/SLICE_16 to I12/SLICE_17:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257      R9C6B.CLK to       R9C6B.Q0 I12/SLICE_16 (from clk_inferred_clock)
ROUTE        19     0.364       R9C6B.Q0 to R9C6A.M0       I12/DFF2 (to clk_inferred_clock)
                  --------
                    0.621   (41.4% logic, 58.6% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I12/SLICE_16:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R9C6B.CLK      clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I12/SLICE_17:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R9C6A.CLK      clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.689ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I22/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I22/DB_out  (to clk_inferred_clock +)

   Delay:               0.622ns  (41.3% logic, 58.7% route), 1 logic levels.

 Constraint Details:

      0.622ns physical path delay I22/SLICE_70 to I22/SLICE_71 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.689ns

 Physical Path Details:

      Data path I22/SLICE_70 to I22/SLICE_71:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257     R9C17B.CLK to      R9C17B.Q0 I22/SLICE_70 (from clk_inferred_clock)
ROUTE        19     0.365      R9C17B.Q0 to R9C17A.M0      I22/DFF2 (to clk_inferred_clock)
                  --------
                    0.622   (41.3% logic, 58.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I22/SLICE_70:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R9C17B.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I22/SLICE_71:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R9C17A.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.689ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I20/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I20/DB_out  (to clk_inferred_clock +)

   Delay:               0.622ns  (41.3% logic, 58.7% route), 1 logic levels.

 Constraint Details:

      0.622ns physical path delay I20/SLICE_88 to I20/SLICE_89 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.689ns

 Physical Path Details:

      Data path I20/SLICE_88 to I20/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257     R5C15B.CLK to      R5C15B.Q0 I20/SLICE_88 (from clk_inferred_clock)
ROUTE        19     0.365      R5C15B.Q0 to R5C15A.M0      I20/DFF2 (to clk_inferred_clock)
                  --------
                    0.622   (41.3% logic, 58.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I20/SLICE_88:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R5C15B.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I20/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R5C15A.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.689ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I21/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I21/DB_out  (to clk_inferred_clock +)

   Delay:               0.622ns  (41.3% logic, 58.7% route), 1 logic levels.

 Constraint Details:

      0.622ns physical path delay I21/SLICE_79 to I21/SLICE_80 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.689ns

 Physical Path Details:

      Data path I21/SLICE_79 to I21/SLICE_80:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257     R3C16B.CLK to      R3C16B.Q0 I21/SLICE_79 (from clk_inferred_clock)
ROUTE        19     0.365      R3C16B.Q0 to R3C16A.M0      I21/DFF2 (to clk_inferred_clock)
                  --------
                    0.622   (41.3% logic, 58.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I21/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R3C16B.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I21/SLICE_80:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R3C16A.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.689ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I24/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I24/DB_out  (to clk_inferred_clock +)

   Delay:               0.622ns  (41.3% logic, 58.7% route), 1 logic levels.

 Constraint Details:

      0.622ns physical path delay I24/SLICE_52 to I24/SLICE_53 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.689ns

 Physical Path Details:

      Data path I24/SLICE_52 to I24/SLICE_53:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257     R5C12B.CLK to      R5C12B.Q0 I24/SLICE_52 (from clk_inferred_clock)
ROUTE        19     0.365      R5C12B.Q0 to R5C12A.M0      I24/DFF2 (to clk_inferred_clock)
                  --------
                    0.622   (41.3% logic, 58.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I24/SLICE_52:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R5C12B.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I24/SLICE_53:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R5C12A.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.689ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I25/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I25/DB_out  (to clk_inferred_clock +)

   Delay:               0.622ns  (41.3% logic, 58.7% route), 1 logic levels.

 Constraint Details:

      0.622ns physical path delay I25/SLICE_43 to I25/SLICE_44 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.689ns

 Physical Path Details:

      Data path I25/SLICE_43 to I25/SLICE_44:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257     R5C18B.CLK to      R5C18B.Q0 I25/SLICE_43 (from clk_inferred_clock)
ROUTE        19     0.365      R5C18B.Q0 to R5C18A.M0      I25/DFF2 (to clk_inferred_clock)
                  --------
                    0.622   (41.3% logic, 58.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I25/SLICE_43:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R5C18B.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I25/SLICE_44:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R5C18A.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.689ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I13/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I13/DB_out  (to clk_inferred_clock +)

   Delay:               0.622ns  (41.3% logic, 58.7% route), 1 logic levels.

 Constraint Details:

      0.622ns physical path delay I13/SLICE_7 to I13/SLICE_8 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.689ns

 Physical Path Details:

      Data path I13/SLICE_7 to I13/SLICE_8:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257      R8C4B.CLK to       R8C4B.Q0 I13/SLICE_7 (from clk_inferred_clock)
ROUTE        19     0.365       R8C4B.Q0 to R8C4A.M0       I13/DFF2 (to clk_inferred_clock)
                  --------
                    0.622   (41.3% logic, 58.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I13/SLICE_7:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R8C4B.CLK      clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I13/SLICE_8:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R8C4A.CLK      clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.690ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I19/DFF2  (from clk_inferred_clock +)
   Destination:    FF         Data in        I19/DB_out  (to clk_inferred_clock +)

   Delay:               0.623ns  (41.3% logic, 58.7% route), 1 logic levels.

 Constraint Details:

      0.623ns physical path delay I19/SLICE_97 to I19/SLICE_98 meets
     -0.067ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.067ns) by 0.690ns

 Physical Path Details:

      Data path I19/SLICE_97 to I19/SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257      R3C5B.CLK to       R3C5B.Q0 I19/SLICE_97 (from clk_inferred_clock)
ROUTE        19     0.366       R3C5B.Q0 to R3C5A.M0       I19/DFF2 (to clk_inferred_clock)
                  --------
                    0.623   (41.3% logic, 58.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I19/SLICE_97:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R3C5B.CLK      clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I19/SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R3C5A.CLK      clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.745ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              I18/q_reg_16  (from clk_inferred_clock +)
   Destination:    FF         Data in        I18/DB_out  (to clk_inferred_clock +)

   Delay:               0.693ns  (37.1% logic, 62.9% route), 1 logic levels.

 Constraint Details:

      0.693ns physical path delay I18/SLICE_156 to I18/SLICE_100 meets
     -0.052ns CE_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.052ns) by 0.745ns

 Physical Path Details:

      Data path I18/SLICE_156 to I18/SLICE_100:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.257     R4C12B.CLK to      R4C12B.Q0 I18/SLICE_156 (from clk_inferred_clock)
ROUTE         3     0.436      R4C12B.Q0 to R4C12A.CE      I18/q_reg_16 (to clk_inferred_clock)
                  --------
                    0.693   (37.1% logic, 62.9% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCInst0 to I18/SLICE_156:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R4C12B.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCInst0 to I18/SLICE_100:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       159     2.474        OSC.OSC to R4C12A.CLK     clk_inferred_clock
                  --------
                    2.474   (0.0% logic, 100.0% route), 0 logic levels.

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "clk_inferred_clock"      |             |             |
38.000000 MHz ;                         |            -|            -|   1  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 7 clocks:

Clock Domain: clk_inferred_clock   Source: OSCInst0.OSC   Loads: 159
   Covered under: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;

   Data transfers from:
   Clock Domain: I16/wb_dat_o_0_sqmuxa   Source: I16/SLICE_289.F0
      Covered under: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;   Transfers: 2

   Clock Domain: I16_state_reg_3   Source: SLICE_143.F1
      Covered under: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;   Transfers: 11

   Clock Domain: I17/state_reg_derived_clock_2   Source: SLICE_102.Q0
      Covered under: FREQUENCY NET "clk_inferred_clock" 38.000000 MHz ;   Transfers: 8

Clock Domain: I16/wb_dat_o_0_sqmuxa   Source: I16/SLICE_289.F0   Loads: 5
   No transfer within this clock domain is found

Clock Domain: I16_state_reg_3   Source: SLICE_143.F1   Loads: 11
   No transfer within this clock domain is found

Clock Domain: I15/spi_clk_o   Source: I15/EFBInst_0.SPISCKO   Loads: 1
   No transfer within this clock domain is found

Clock Domain: I15/spi_clk_i   Source: spi_clk.PAD   Loads: 1
   No transfer within this clock domain is found

Clock Domain: I17/state_reg_derived_clock_5   Source: SLICE_145.Q0   Loads: 4
   No transfer within this clock domain is found

Clock Domain: I17/state_reg_derived_clock_2   Source: SLICE_102.Q0   Loads: 5
   No transfer within this clock domain is found


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 5178 paths, 1 nets, and 1652 connections (80.2% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)