Static Timing Analysis

Project : Design01
Build Time : 10/20/15 11:44:18
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Ext_CP_Clk ADC_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_Ext_CP_Clk(routed) ADC_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ADC_theACLK(fixed-function) ADC_theACLK(fixed-function) 631.579 kHz 631.579 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 61.346 MHz
UART_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 57.402 MHz
ADC_theACLK CyMASTER_CLK 631.579 kHz 631.579 kHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
\ADC:DSM\/dec_clock \ADC:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 61.346 MHz 16.301 25.366
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.244
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 84.904 MHz 11.778 29.889
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 6.259
macrocell22 U(0,1) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 84.991 MHz 11.766 29.901
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 6.247
macrocell23 U(0,1) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 92.911 MHz 10.763 30.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.244
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 92.911 MHz 10.763 30.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.244
macrocell25 U(1,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 95.850 MHz 10.433 31.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 4.914
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 95.850 MHz 10.433 31.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 4.914
macrocell24 U(0,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.402 MHz 17.421 1065.912
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 4.336
macrocell2 U(0,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.295
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.728 MHz 16.467 1066.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 3.382
macrocell2 U(0,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.295
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.531 MHz 15.992 1067.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,1) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 2.907
macrocell2 U(0,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.295
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 63.383 MHz 15.777 1067.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,0) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 3.568
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 64.725 MHz 15.450 1067.883
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 3.425
macrocell2 U(0,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.295
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 65.240 MHz 15.328 1068.005
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 3.119
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 65.781 MHz 15.202 1068.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 2.993
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 65.785 MHz 15.201 1068.132
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 2.992
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 71.633 MHz 13.960 1069.373
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,1) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 3.662
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 73.137 MHz 13.673 1069.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,1) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 3.375
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 6.923
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 4.914
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 6.923
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 4.914
macrocell24 U(0,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 7.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.244
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 7.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.244
macrocell25 U(1,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 8.256
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 6.247
macrocell23 U(0,1) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 8.268
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 6.259
macrocell22 U(0,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 12.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_17 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.244
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.510
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.260
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.798
macrocell10 U(1,1) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.798
macrocell11 U(1,1) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 3.007
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.817
macrocell13 U(0,1) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 3.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.684
macrocell17 U(0,0) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_5 3.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_5 2.684
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 3.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 2.688
macrocell17 U(0,0) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_6 3.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_6 2.688
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_0\/main_5 3.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_0\/main_5 2.721
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_6 3.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_6 2.721
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 31.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_12/main_0 4.483
macrocell1 U(1,0) 1 Net_12 Net_12/main_0 Net_12/q 3.350
Route 1 Net_12 Net_12/q Tx_1(0)/pin_input 5.431
iocell2 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000