\UART:BUART:rx_state_3\/q |
\UART:BUART:sRX:RxBitCounter\/load |
54.401 MHz |
18.382 |
1064.951 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell13 |
U(0,0) |
1 |
\UART:BUART:rx_state_3\ |
\UART:BUART:rx_state_3\/clock_0 |
\UART:BUART:rx_state_3\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_3\ |
\UART:BUART:rx_state_3\/q |
\UART:BUART:rx_counter_load\/main_1 |
6.173 |
macrocell7 |
U(0,0) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_1 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_1\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
58.295 MHz |
17.154 |
1066.179 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell20 |
U(0,1) |
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/clock_0 |
\UART:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/q |
\UART:BUART:counter_load_not\/main_0 |
4.072 |
macrocell2 |
U(1,1) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_0 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.292 |
datapathcell3 |
U(1,1) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_0\/q |
\UART:BUART:sRX:RxBitCounter\/load |
59.263 MHz |
16.874 |
1066.459 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell11 |
U(0,0) |
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/clock_0 |
\UART:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/q |
\UART:BUART:rx_counter_load\/main_0 |
4.665 |
macrocell7 |
U(0,0) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_0 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
62.131 MHz |
16.095 |
1067.238 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell3 |
U(1,1) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART:BUART:tx_bitclk_enable_pre\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:counter_load_not\/main_2 |
4.073 |
macrocell2 |
U(1,1) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_2 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.292 |
datapathcell3 |
U(1,1) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_2\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
62.298 MHz |
16.052 |
1067.281 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell21 |
U(0,1) |
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/clock_0 |
\UART:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/q |
\UART:BUART:counter_load_not\/main_3 |
2.970 |
macrocell2 |
U(1,1) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_3 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.292 |
datapathcell3 |
U(1,1) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_0\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
62.653 MHz |
15.961 |
1067.372 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell19 |
U(1,1) |
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/clock_0 |
\UART:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/q |
\UART:BUART:counter_load_not\/main_1 |
2.879 |
macrocell2 |
U(1,1) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_1 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.292 |
datapathcell3 |
U(1,1) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_address_detected\/q |
\UART:BUART:sRX:RxBitCounter\/load |
62.712 MHz |
15.946 |
1067.387 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell5 |
U(0,0) |
1 |
\UART:BUART:rx_address_detected\ |
\UART:BUART:rx_address_detected\/clock_0 |
\UART:BUART:rx_address_detected\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_address_detected\ |
\UART:BUART:rx_address_detected\/q |
\UART:BUART:rx_counter_load\/main_3 |
3.737 |
macrocell7 |
U(0,0) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_3 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_2\/q |
\UART:BUART:sRX:RxBitCounter\/load |
63.898 MHz |
15.650 |
1067.683 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell12 |
U(0,0) |
1 |
\UART:BUART:rx_state_2\ |
\UART:BUART:rx_state_2\/clock_0 |
\UART:BUART:rx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_2\ |
\UART:BUART:rx_state_2\/q |
\UART:BUART:rx_counter_load\/main_2 |
3.441 |
macrocell7 |
U(0,0) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_2 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.249 |
count7cell |
U(0,0) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:sTX:TxSts\/status_0 |
64.529 MHz |
15.497 |
1067.836 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(1,0) |
1 |
\UART:BUART:sTX:TxShifter:u0\ |
\UART:BUART:sTX:TxShifter:u0\/clock |
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
3.580 |
Route |
|
1 |
\UART:BUART:tx_fifo_empty\ |
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:tx_status_0\/main_3 |
5.191 |
macrocell22 |
U(1,1) |
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/main_3 |
\UART:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/q |
\UART:BUART:sTX:TxSts\/status_0 |
2.876 |
statusicell2 |
U(1,0) |
1 |
\UART:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_0\/q |
\UART:BUART:sRX:RxShifter:u0\/cs_addr_1 |
70.557 MHz |
14.173 |
1069.160 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell11 |
U(0,0) |
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/clock_0 |
\UART:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/q |
\UART:BUART:sRX:RxShifter:u0\/cs_addr_1 |
6.913 |
datapathcell1 |
U(0,1) |
1 |
\UART:BUART:sRX:RxShifter:u0\ |
|
SETUP |
6.010 |
Clock |
|
|
|
|
Skew |
0.000 |
|