/* * Device Tree Source for AM33XX SoC * * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include / { compatible = "ti,am33xx"; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; chosen { }; aliases: aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; d_can0 = &dcan0; d_can1 = &dcan1; usb0 = &usb0; usb1 = &usb1; phy0 = &usb0_phy; phy1 = &usb1_phy; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1; spi1 = &spi0; spi2 = &spi1; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a8"; enable-method = "ti,am3352"; device_type = "cpu"; reg = <0>; operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ cpu-idle-states = <&mpu_gate>; }; idle-states { mpu_gate: mpu_gate { compatible = "arm,idle-state"; entry-latency-us = <40>; exit-latency-us = <90>; min-residency-us = <300>; ti,idle-wkup-m3; }; }; }; cpu0_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_conf>; /* * The three following nodes are marked with opp-suspend * because the can not be enabled simultaneously on a * single SoC. */ opp50-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; opp-supported-hw = <0x06 0x0010>; opp-suspend; }; opp100-275000000 { opp-hz = /bits/ 64 <275000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x01 0x00FF>; opp-suspend; }; opp100-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x06 0x0020>; opp-suspend; }; opp100-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x01 0xFFFF>; }; opp100-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x06 0x0040>; }; opp120-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0x01 0xFFFF>; }; opp120-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0x06 0x0080>; }; oppturbo-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0x01 0xFFFF>; }; oppturbo-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0x06 0x0100>; }; oppnitro-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1325000 1298500 1351500>; opp-supported-hw = <0x04 0x0200>; }; }; pmu { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; }; /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap3-mpu"; ti,hwmods = "mpu"; pm-sram = <&pm_sram_code &pm_sram_data>; }; }; /* * XXX: Use a flat representation of the AM33XX interconnect. * The real AM33XX interconnect network is quite complex. Since * it will not bring real advantage to represent that in DT * for the moment, just use a fake OCP (Open Core Protocol) bus entry to represent * the whole bus hierarchy. */ ocp: ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; l4_wkup: l4_wkup@44c00000 { compatible = "ti,am3-l4-wkup", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x44c00000 0x280000>; wkup_m3: wkup_m3@100000 { compatible = "ti,am3352-wkup-m3"; reg = <0x100000 0x4000>, <0x180000 0x2000>; reg-names = "umem", "dmem"; ti,hwmods = "wkup_m3"; ti,pm-firmware = "am335x-pm-firmware.elf"; }; prcm: prcm@200000 { compatible = "ti,am3-prcm"; reg = <0x200000 0x4000>; prcm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prcm_clockdomains: clockdomains { }; }; scm: scm@210000 { compatible = "ti,am3-scm", "simple-bus"; reg = <0x210000 0x2000>; #address-cells = <1>; #size-cells = <1>; #pinctrl-cells = <1>; ranges = <0 0x210000 0x2000>; am33xx_pinmux: pinmux@800 { compatible = "pinctrl-single"; reg = <0x800 0x238>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7f>; }; scm_conf: scm_conf@0 { compatible = "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x800>; scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; }; wkup_m3_ipc: wkup_m3_ipc@1324 { compatible = "ti,am3352-wkup-m3-ipc"; reg = <0x1324 0x24>; interrupts = <78>; ti,rproc = <&wkup_m3>; mboxes = <&mailbox &mbox_wkupm3>; }; edma_xbar: dma-router@f90 { compatible = "ti,am335x-edma-crossbar"; reg = <0xf90 0x40>; #dma-cells = <3>; dma-requests = <32>; dma-masters = <&edma>; }; scm_clockdomains: clockdomains { }; }; }; intc: interrupt-controller@48200000 { compatible = "ti,am33xx-intc"; interrupt-controller; #interrupt-cells = <1>; reg = <0x48200000 0x1000>; }; // edma (enhanced direct memory access) edma: edma@49000000 { compatible = "ti,edma3-tpcc"; ti,hwmods = "tpcc"; reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, <&edma_tptc2 0>; ti,edma-memcpy-channels = <20 21>; }; edma_tptc0: tptc@49800000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc0"; reg = <0x49800000 0x100000>; interrupts = <112>; interrupt-names = "edma3_tcerrint"; }; edma_tptc1: tptc@49900000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc1"; reg = <0x49900000 0x100000>; interrupts = <113>; interrupt-names = "edma3_tcerrint"; }; edma_tptc2: tptc@49a00000 { compatible = "ti,edma3-tptc"; ti,hwmods = "tptc2"; reg = <0x49a00000 0x100000>; interrupts = <114>; interrupt-names = "edma3_tcerrint"; }; emif: emif@4c000000 { compatible = "ti,emif-am3352"; reg = <0x4C000000 0x1000>; sram = <&pm_sram_code &pm_sram_data>; }; gpio0: gpio@44e07000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x44e07000 0x1000>; interrupts = <96>; gpio-line-names = "MDIO_DATA", // 0 "MDIO_CLK", // 1 "SPI0_SCLK", // 2 "SPI0_D0", // 3 "SPI0_D1", // 4 "SPI0_CS0", // 5 "SPI0_CS1", // 6 "ECAP0_IN_PWM0_OUT", // 7 "LCD_DATA12", // 8 "LCD_DATA13", // 9 "LCD_DATA14", // 10 "LCD_DATA15", // 11 "UART1_CTSN", // 12 "UART1_RTSN", // 13 "UART1_RXD", // 14 "UART1_TXD", // 15 "GMII1_TXD3", // 16 "GMII1_TXD2", // 17 "USB0_DRVVBUS", // 18 "XDMA_EVENT_INTR0", // 19 "XDMA_EVENT_INTR1", // 20 "GMII1_TXD1", // 21 "GPMC_AD8", // 22 "GPMC_AD9", // 23 "NC", // 24 "NC", // 25 "GPMC_AD10", // 26 "GPMC_AD11", // 27 "GMII1_TXD0", // 28 "RMII1_REFCLK", // 29 "GPMC_WAIT0", // 30 "GPMC_WPN"; // 31 }; gpio1: gpio@4804c000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4804c000 0x1000>; interrupts = <98>; gpio-line-names = "GPMC_AD0", // 0 "GPMC_AD1", // 1 "GPMC_AD2", // 2 "GPMC_AD3", // 3 "GPMC_AD4", // 4 "GPMC_AD5", // 5 "GPMC_AD6", // 6 "GPMC_AD7", // 7 "UART0_CTSN", // 8 "UART0_RTSN", // 9 "UART0_RXD", // 10 "UART0_TXD", // 11 "GPMC_AD12", // 12 "GPMC_AD13", // 13 "GPMC_AD14", // 14 "GPMC_AD15", // 15 "GPMC_A0", // 16 "GPMC_A1", // 17 "GPMC_A2", // 18 "GPMC_A3", // 19 "GPMC_A4", // 20 "GPMC_A5", // 21 "GPMC_A6", // 22 "GPMC_A7", // 23 "GPMC_A8", // 24 "GPMC_A9", // 25 "GPMC_A10", // 26 "GPMC_A11", // 27 "GPMC_BE1N", // 28 "GPMC_CSN0", // 29 "GPMC_CSN1", // 30 "GPMC_CSN2"; // 31 }; gpio2: gpio@481ac000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x481ac000 0x1000>; interrupts = <32>; gpio-line-names = "GPMC_CSN3", // 0 "GPMC_CLK", // 1 "GPMC_ADVN_ALE", // 2 "GPMC_OEN_REN", // 3 "GPMC_WEN", // 4 "GPMC_BE0N_CLE", // 5 "LCD_DATA0", // 6 "LCD_DATA1", // 7 "LCD_DATA2", // 8 "LCD_DATA3", // 9 "LCD_DATA4", // 10 "LCD_DATA5", // 11 "LCD_DATA6", // 12 "LCD_DATA7", // 13 "LCD_DATA8", // 14 "LCD_DATA9", // 15 "LCD_DATA10", // 16 "LCD_DATA11", // 17 "GMII1_RXD3", // 18 "GMII1_RXD2", // 19 "GMII1_RXD1", // 20 "GMII1_RXD0", // 21 "LCD_VSYNC", // 22 "LCD_HSYNC", // 23 "LCD_PCLK", // 24 "LCD_AC_BIAS_EN", // 25 "MMC0_DAT3", // 26 "MMC0_DAT2", // 27 "MMC0_DAT1", // 28 "MMC0_DAT0", // 29 "MMC0_CLK", // 30 "MMC0_CMD"; // 31 }; gpio3: gpio@481ae000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x481ae000 0x1000>; interrupts = <62>; gpio-line-names = "GMII1_COL", // 0 "GMII1_CRS", // 1 "GMII1_RXER", // 2 "GMII1_TXEN", // 3 "GMII1_RXDV", // 4 "I2C0_SDA", // 5 "I2C0_SCL", // 6 "EMU0", // 7 "EMU1", // 8 "GMII1_TXCLK", // 9 "GMII1_RXCLK", // 10 "NC", // 11 "NC", // 12 "USB1_DRVVBUS", // 13 "MCASP0_ACLKX", // 14 "MCASP0_FSX", // 15 "MCASP0_AXR0", // 16 "MCASP0_AHCLKR", // 17 "MCASP0_ACLKR", // 18 "MCASP0_FSR", // 19 "MCASP0_AXR1", // 20 "MCASP0_AHCLKX", // 21 "NC", // 22 "NC", // 23 "NC", // 24 "NC", // 25 "NC", // 26 "NC", // 27 "NC", // 28 "NC", // 29 "NC", // 30 "NC"; // 31 }; uart0: serial@44e09000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; reg = <0x44e09000 0x2000>; interrupts = <72>; status = "disabled"; dmas = <&edma 26 0>, <&edma 27 0>; dma-names = "tx", "rx"; }; uart1: serial@48022000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; reg = <0x48022000 0x2000>; interrupts = <73>; status = "disabled"; dmas = <&edma 28 0>, <&edma 29 0>; dma-names = "tx", "rx"; }; uart2: serial@48024000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; reg = <0x48024000 0x2000>; interrupts = <74>; status = "disabled"; dmas = <&edma 30 0>, <&edma 31 0>; dma-names = "tx", "rx"; }; uart3: serial@481a6000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; reg = <0x481a6000 0x2000>; interrupts = <44>; status = "disabled"; }; uart4: serial@481a8000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart5"; clock-frequency = <48000000>; reg = <0x481a8000 0x2000>; interrupts = <45>; status = "disabled"; }; uart5: serial@481aa000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart6"; clock-frequency = <48000000>; reg = <0x481aa000 0x2000>; interrupts = <46>; status = "disabled"; }; i2c0: i2c@44e0b000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; reg = <0x44e0b000 0x1000>; interrupts = <70>; status = "disabled"; }; i2c1: i2c@4802a000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; reg = <0x4802a000 0x1000>; interrupts = <71>; status = "disabled"; }; i2c2: i2c@4819c000 { compatible = "ti,omap4-i2c"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; reg = <0x4819c000 0x1000>; interrupts = <30>; status = "disabled"; }; mmc1: mmc@48060000 { compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; ti,needs-special-hs-handling; dmas = <&edma_xbar 24 0 0 &edma_xbar 25 0 0>; dma-names = "tx", "rx"; interrupts = <64>; reg = <0x48060000 0x1000>; status = "disabled"; }; mmc2: mmc@481d8000 { compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc2"; ti,needs-special-reset; dmas = <&edma 2 0 &edma 3 0>; dma-names = "tx", "rx"; interrupts = <28>; reg = <0x481d8000 0x1000>; status = "disabled"; }; mmc3: mmc@47810000 { compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc3"; ti,needs-special-reset; interrupts = <29>; reg = <0x47810000 0x1000>; status = "disabled"; }; hwspinlock: spinlock@480ca000 { compatible = "ti,omap4-hwspinlock"; reg = <0x480ca000 0x1000>; ti,hwmods = "spinlock"; #hwlock-cells = <1>; }; wdt2: wdt@44e35000 { compatible = "ti,omap3-wdt"; ti,hwmods = "wd_timer2"; reg = <0x44e35000 0x1000>; interrupts = <91>; }; dcan0: can@481cc000 { compatible = "ti,am3352-d_can"; ti,hwmods = "d_can0"; reg = <0x481cc000 0x2000>; clocks = <&dcan0_fck>; clock-names = "fck"; syscon-raminit = <&scm_conf 0x644 0>; interrupts = <52>; status = "disabled"; }; dcan1: can@481d0000 { compatible = "ti,am3352-d_can"; ti,hwmods = "d_can1"; reg = <0x481d0000 0x2000>; clocks = <&dcan1_fck>; clock-names = "fck"; syscon-raminit = <&scm_conf 0x644 1>; interrupts = <55>; status = "disabled"; }; mailbox: mailbox@480c8000 { compatible = "ti,omap4-mailbox"; reg = <0x480c8000 0x200>; interrupts = <77>; ti,hwmods = "mailbox"; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; }; }; timer1: timer@44e31000 { compatible = "ti,am335x-timer-1ms"; reg = <0x44e31000 0x400>; interrupts = <67>; ti,hwmods = "timer1"; ti,timer-alwon; }; timer2: timer@48040000 { compatible = "ti,am335x-timer"; reg = <0x48040000 0x400>; interrupts = <68>; ti,hwmods = "timer2"; }; timer3: timer@48042000 { compatible = "ti,am335x-timer"; reg = <0x48042000 0x400>; interrupts = <69>; ti,hwmods = "timer3"; }; timer4: timer@48044000 { compatible = "ti,am335x-timer"; reg = <0x48044000 0x400>; interrupts = <92>; ti,hwmods = "timer4"; ti,timer-pwm; }; timer5: timer@48046000 { compatible = "ti,am335x-timer"; reg = <0x48046000 0x400>; interrupts = <93>; ti,hwmods = "timer5"; ti,timer-pwm; }; timer6: timer@48048000 { compatible = "ti,am335x-timer"; reg = <0x48048000 0x400>; interrupts = <94>; ti,hwmods = "timer6"; ti,timer-pwm; }; timer7: timer@4804a000 { compatible = "ti,am335x-timer"; reg = <0x4804a000 0x400>; interrupts = <95>; ti,hwmods = "timer7"; ti,timer-pwm; }; rtc: rtc@44e3e000 { compatible = "ti,am3352-rtc", "ti,da830-rtc"; reg = <0x44e3e000 0x1000>; interrupts = <75 76>; ti,hwmods = "rtc"; clocks = <&clkdiv32k_ick>; clock-names = "int-clk"; }; spi0: spi@48030000 { compatible = "ti,omap4-mcspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x48030000 0x400>; interrupts = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; dmas = <&edma 16 0 &edma 17 0 &edma 18 0 &edma 19 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; spi1: spi@481a0000 { compatible = "ti,omap4-mcspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x481a0000 0x400>; interrupts = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; dmas = <&edma 42 0 &edma 43 0 &edma 44 0 &edma 45 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; usb: usb@47400000 { compatible = "ti,am33xx-usb"; reg = <0x47400000 0x1000>; ranges; #address-cells = <1>; #size-cells = <1>; ti,hwmods = "usb_otg_hs"; status = "disabled"; usb_ctrl_mod: control@44e10620 { compatible = "ti,am335x-usb-ctrl-module"; reg = <0x44e10620 0x10 0x44e10648 0x4>; reg-names = "phy_ctrl", "wakeup"; status = "disabled"; }; usb0_phy: usb-phy@47401300 { compatible = "ti,am335x-usb-phy"; reg = <0x47401300 0x100>; reg-names = "phy"; status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; #phy-cells = <0>; }; usb0: usb@47401000 { compatible = "ti,musb-am33xx"; status = "disabled"; reg = <0x47401400 0x400 0x47401000 0x200>; reg-names = "mc", "control"; interrupts = <18>; interrupt-names = "mc"; dr_mode = "otg"; mentor,multipoint = <1>; mentor,num-eps = <16>; mentor,ram-bits = <12>; mentor,power = <500>; phys = <&usb0_phy>; dmas = <&cppi41dma 0 0 &cppi41dma 1 0 &cppi41dma 2 0 &cppi41dma 3 0 &cppi41dma 4 0 &cppi41dma 5 0 &cppi41dma 6 0 &cppi41dma 7 0 &cppi41dma 8 0 &cppi41dma 9 0 &cppi41dma 10 0 &cppi41dma 11 0 &cppi41dma 12 0 &cppi41dma 13 0 &cppi41dma 14 0 &cppi41dma 0 1 &cppi41dma 1 1 &cppi41dma 2 1 &cppi41dma 3 1 &cppi41dma 4 1 &cppi41dma 5 1 &cppi41dma 6 1 &cppi41dma 7 1 &cppi41dma 8 1 &cppi41dma 9 1 &cppi41dma 10 1 &cppi41dma 11 1 &cppi41dma 12 1 &cppi41dma 13 1 &cppi41dma 14 1>; dma-names = "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", "tx14", "tx15"; }; usb1_phy: usb-phy@47401b00 { compatible = "ti,am335x-usb-phy"; reg = <0x47401b00 0x100>; reg-names = "phy"; status = "disabled"; ti,ctrl_mod = <&usb_ctrl_mod>; #phy-cells = <0>; }; usb1: usb@47401800 { compatible = "ti,musb-am33xx"; status = "disabled"; reg = <0x47401c00 0x400 0x47401800 0x200>; reg-names = "mc", "control"; interrupts = <19>; interrupt-names = "mc"; dr_mode = "otg"; mentor,multipoint = <1>; mentor,num-eps = <16>; mentor,ram-bits = <12>; mentor,power = <500>; phys = <&usb1_phy>; dmas = <&cppi41dma 15 0 &cppi41dma 16 0 &cppi41dma 17 0 &cppi41dma 18 0 &cppi41dma 19 0 &cppi41dma 20 0 &cppi41dma 21 0 &cppi41dma 22 0 &cppi41dma 23 0 &cppi41dma 24 0 &cppi41dma 25 0 &cppi41dma 26 0 &cppi41dma 27 0 &cppi41dma 28 0 &cppi41dma 29 0 &cppi41dma 15 1 &cppi41dma 16 1 &cppi41dma 17 1 &cppi41dma 18 1 &cppi41dma 19 1 &cppi41dma 20 1 &cppi41dma 21 1 &cppi41dma 22 1 &cppi41dma 23 1 &cppi41dma 24 1 &cppi41dma 25 1 &cppi41dma 26 1 &cppi41dma 27 1 &cppi41dma 28 1 &cppi41dma 29 1>; dma-names = "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", "tx14", "tx15"; }; cppi41dma: dma-controller@47402000 { compatible = "ti,am3359-cppi41"; reg = <0x47400000 0x1000 0x47402000 0x1000 0x47403000 0x1000 0x47404000 0x4000>; reg-names = "glue", "controller", "scheduler", "queuemgr"; interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; #dma-channels = <30>; #dma-requests = <256>; status = "disabled"; }; }; epwmss0: epwmss@48300000 { compatible = "ti,am33xx-pwmss"; reg = <0x48300000 0x10>; ti,hwmods = "epwmss0"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x48300100 0x48300100 0x80 /* ECAP */ 0x48300180 0x48300180 0x80 /* EQEP */ 0x48300200 0x48300200 0x80>; /* EHRPWM */ ecap0: ecap@48300100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <31>; interrupt-names = "ecap0"; status = "disabled"; }; eqep0: eqep@48300180 { compatible = "ti,am33xx-eqep"; reg = <0x48300180 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupt-parent = <&intc>; interrupts = <79>; status = "disabled"; }; ehrpwm0: pwm@48300200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; epwmss1: epwmss@48302000 { compatible = "ti,am33xx-pwmss"; reg = <0x48302000 0x10>; ti,hwmods = "epwmss1"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x48302100 0x48302100 0x80 /* ECAP */ 0x48302180 0x48302180 0x80 /* EQEP */ 0x48302200 0x48302200 0x80>; /* EHRPWM */ ecap1: ecap@48302100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <47>; interrupt-names = "ecap1"; status = "disabled"; }; eqep1: eqep@48302180 { compatible = "ti,am33xx-eqep"; reg = <0x48302180 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupt-parent = <&intc>; interrupts = <88>; status = "disabled"; }; ehrpwm1: pwm@48302200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; epwmss2: epwmss@48304000 { compatible = "ti,am33xx-pwmss"; reg = <0x48304000 0x10>; ti,hwmods = "epwmss2"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; ranges = <0x48304100 0x48304100 0x80 /* ECAP */ 0x48304180 0x48304180 0x80 /* EQEP */ 0x48304200 0x48304200 0x80>; /* EHRPWM */ ecap2: ecap@48304100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48304100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <61>; interrupt-names = "ecap2"; status = "disabled"; }; eqep2: eqep@48304180 { compatible = "ti,am33xx-eqep"; reg = <0x48304180 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupt-parent = <&intc>; interrupts = <89>; status = "disabled"; }; ehrpwm2: pwm@48304200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; }; }; mac: ethernet@4a100000 { compatible = "ti,am335x-cpsw","ti,cpsw"; ti,hwmods = "cpgmac0"; clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; bd_ram_size = <0x2000>; mac_control = <0x20>; slaves = <1>; active_slave = <0>; cpts_clock_mult = <0x80000000>; cpts_clock_shift = <29>; reg = <0x4a100000 0x800 0x4a101200 0x100>; #address-cells = <1>; #size-cells = <1>; /* * c0_rx_thresh_pend * c0_rx_pend * c0_tx_pend * c0_misc_pend */ interrupts = <40 41 42 43>; ranges; syscon = <&scm_conf>; status = "disabled"; davinci_mdio: mdio@4a101000 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "davinci_mdio"; bus_freq = <1000000>; reg = <0x4a101000 0x100>; status = "disabled"; }; cpsw_emac0: slave@4a100200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; }; cpsw_emac1: slave@4a100300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; }; phy_sel: cpsw-phy-sel@44e10650 { compatible = "ti,am3352-cpsw-phy-sel"; reg= <0x44e10650 0x4>; reg-names = "gmii-sel"; }; }; ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x10000>; /* 64k */ ranges = <0x0 0x40300000 0x10000>; #address-cells = <1>; #size-cells = <1>; pm_sram_code: pm-sram-code@0 { compatible = "ti,sram"; reg = <0x0 0x1000>; protect-exec; }; pm_sram_data: pm-sram-data@1000 { compatible = "ti,sram"; reg = <0x1000 0x1000>; pool; }; }; pruss_soc_bus: pruss_soc_bus@4a326004 { compatible = "ti,am3356-pruss-soc-bus"; reg = <0x4a326004 0x4>; ti,hwmods = "pruss"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4a300000 0x80000>; status = "disabled"; pruss: pruss@0 { compatible = "ti,am3356-pruss"; reg = <0x0 0x80000>; interrupts = <20 21 22 23 24 25 26 27>; interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9"; #address-cells = <1>; #size-cells = <1>; ranges; status = "disabled"; pruss_mem: memories@0 { reg = <0x0 0x2000>, <0x2000 0x2000>, <0x10000 0x3000>; reg-names = "dram0", "dram1", "shrdram2"; }; pruss_cfg: cfg@26000 { compatible = "syscon"; reg = <0x26000 0x2000>; }; pruss_iep: iep@2e000 { compatible = "syscon"; reg = <0x2e000 0x31c>; }; pruss_mii_rt: mii_rt@32000 { compatible = "syscon"; reg = <0x32000 0x58>; }; pruss_intc: intc@20000 { compatible = "ti,am3356-pruss-intc"; reg = <0x20000 0x2000>; reg-names = "intc"; interrupt-controller; #interrupt-cells = <1>; }; pru0: pru@34000 { compatible = "ti,am3356-pru"; reg = <0x34000 0x2000>, <0x22000 0x400>, <0x22400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am335x-pru0-fw"; interrupt-parent = <&pruss_intc>; interrupts = <16>, <17>; interrupt-names = "vring", "kick"; }; pru1: pru@38000 { compatible = "ti,am3356-pru"; reg = <0x38000 0x2000>, <0x24000 0x400>, <0x24400 0x100>; reg-names = "iram", "control", "debug"; firmware-name = "am335x-pru1-fw"; interrupt-parent = <&pruss_intc>; interrupts = <18>, <19>; interrupt-names = "vring", "kick"; }; pruss_mdio: mdio@32400 { compatible = "ti,davinci_mdio"; reg = <0x32400 0x90>; clocks = <&dpll_core_m4_ck>; clock-names = "fck"; bus_freq = <1000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; }; elm: elm@48080000 { compatible = "ti,am3352-elm"; reg = <0x48080000 0x2000>; interrupts = <4>; ti,hwmods = "elm"; status = "disabled"; }; lcdc: lcdc@4830e000 { compatible = "ti,am33xx-tilcdc"; reg = <0x4830e000 0x1000>; interrupts = <36>; ti,hwmods = "lcdc"; status = "disabled"; }; tscadc: tscadc@44e0d000 { compatible = "ti,am3359-tscadc"; reg = <0x44e0d000 0x1000>; interrupts = <16>; ti,hwmods = "adc_tsc"; status = "disabled"; dmas = <&edma 53 0>, <&edma 57 0>; dma-names = "fifo0", "fifo1"; tsc { compatible = "ti,am3359-tsc"; }; am335x_adc: adc { #io-channel-cells = <1>; compatible = "ti,am3359-adc"; }; }; gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; ti,no-idle-on-init; reg = <0x50000000 0x2000>; interrupts = <100>; dmas = <&edma 52 0>; dma-names = "rxtx"; gpmc,num-cs = <7>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; sham: sham@53100000 { compatible = "ti,omap4-sham"; ti,hwmods = "sham"; reg = <0x53100000 0x200>; interrupts = <109>; dmas = <&edma 36 0>; dma-names = "rx"; }; aes: aes@53500000 { compatible = "ti,omap4-aes"; ti,hwmods = "aes"; reg = <0x53500000 0xa0>; interrupts = <103>; dmas = <&edma 6 0>, <&edma 5 0>; dma-names = "tx", "rx"; }; mcasp0: mcasp@48038000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp0"; reg = <0x48038000 0x2000>, <0x46000000 0x400000>; reg-names = "mpu", "dat"; interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 8 2>, <&edma 9 2>; dma-names = "tx", "rx"; }; mcasp1: mcasp@4803c000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp1"; reg = <0x4803c000 0x2000>, <0x46400000 0x400000>; reg-names = "mpu", "dat"; interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; dmas = <&edma 10 2>, <&edma 11 2>; dma-names = "tx", "rx"; }; rng: rng@48310000 { compatible = "ti,omap4-rng"; ti,hwmods = "rng"; reg = <0x48310000 0x2000>; interrupts = <111>; }; /* * The SGX is disabled by default because it is an optional * module and only some AM335x variants contain this module, * such as AM3358 and AM3357. The status should be overwritten * as "OK" at the corresponding board.dts. */ sgx: sgx@56000000 { compatible = "ti,am3352-sgx530", "img,sgx530"; ti,hwmods = "gfx"; reg = <0x56000000 0x10000>; interrupts = <37>; clocks = <&gfx_fck_div_ck>; clock-names = "fclk"; status = "disabled"; }; }; }; /include/ "am33xx-clocks.dtsi"