Static Timing Analysis

Project : Design01
Build Time : 06/17/16 10:47:59
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 46.611 MHz
UART_IntClock CyHFCLK 923.077 kHz 923.077 kHz 44.066 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 46.611 MHz 21.454 20.213
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.987
macrocell6 U(0,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.860
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 73.833 MHz 13.544 28.123
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 5.987
macrocell22 U(0,1) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 73.844 MHz 13.542 28.125
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 5.985
macrocell21 U(0,1) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 78.784 MHz 12.693 28.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.136
macrocell15 U(0,0) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 78.784 MHz 12.693 28.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.136
macrocell23 U(0,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 78.939 MHz 12.668 28.999
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 5.111
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 78.939 MHz 12.668 28.999
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.111
macrocell24 U(0,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.066 MHz 22.693 1060.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,1) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.281
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.066 MHz 21.708 1061.625
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 3.546
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.243 MHz 21.625 1061.708
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.213
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.548 MHz 21.483 1061.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 3.071
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 56.007 MHz 17.855 1065.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.246
macrocell7 U(1,0) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 5.409
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 60.266 MHz 16.593 1066.740
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,1) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 3.923
macrocell6 U(0,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.860
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 61.847 MHz 16.169 1067.164
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 3.655
macrocell3 U(0,1) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.314
statusicell1 U(0,1) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 63.383 MHz 15.777 1067.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,1) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 3.107
macrocell6 U(0,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.860
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 63.922 MHz 15.644 1067.689
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,0) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 4.569
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxSts\/status_4 70.862 MHz 14.112 1069.221
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,0) 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/clock_0 \UART:BUART:rx_load_fifo\/q 1.250
Route 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/q \UART:BUART:rx_status_4\/main_0 2.533
macrocell7 U(1,0) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_0 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 5.409
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 7.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 5.111
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 7.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.111
macrocell24 U(0,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 7.876
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.136
macrocell15 U(0,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 7.876
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.136
macrocell23 U(0,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 8.725
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 5.985
macrocell21 U(0,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 8.727
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 5.987
macrocell22 U(0,1) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 14.937
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.987
macrocell6 U(0,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.860
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,0) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.252
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 3.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/clock_0 \UART:BUART:rx_last\/q 1.250
Route 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 2.240
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell9 U(1,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.306
macrocell9 U(1,1) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 3.788
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.788
macrocell12 U(1,1) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_4 3.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_4 2.541
macrocell15 U(0,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_load_fifo\/main_4 3.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_load_fifo\/main_4 2.541
macrocell16 U(0,0) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_3\/main_4 3.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_3\/main_4 2.541
macrocell17 U(0,0) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_status_3\/main_4 3.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_status_3\/main_4 2.541
macrocell23 U(0,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxShifter:u0\/f0_load 3.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,0) 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/clock_0 \UART:BUART:rx_load_fifo\/q 1.250
Route 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxShifter:u0\/f0_load 2.542
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_2\/main_4 3.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_2\/main_4 2.542
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 28.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_21/main_0 3.194
macrocell1 U(1,0) 1 Net_21 Net_21/main_0 Net_21/q 3.350
Route 1 Net_21 Net_21/q Tx_1(0)/pin_input 5.337
iocell2 P1[6] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.420
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000