I2C Master (VHDL)

[APDahlen]

Hello ozanaidan,

Yes, use of a synchronizer is generally a good idea when crossing clock boundaries. An example is the SPI clock signal which should be synchronized upon entering the FPGA.

Please accept this Verilog implementation. Most FPGA synthesis tools will accept Verilog or VHDL.

Best Wishes,

APDahlen

Implementing a Clock Boundary Synchronizer in Verilog

In this post we will explore a Verilog description of a clock synchronizer. From your introduction to digital electronics, you may recall the concept of metastability. This is an undesirable condition where a digital signal enters an indeterminate state; neither one nor zero. Let’s start by defining a few terms: Clock boundary: Many logic designs are designed to be synchronous which implies that all logic moves with the same heartbeat. In an FPGA this is implemented as a series of registers.…