Electrostatic discharge protection on pull-up pin


I am posting this on behalf of a customer, David :

I need help using the digikey PN SESD7L5.0DT5GOSCT-ND

SESD7L5.0DT5G https://www.digikey.com/en/products/detail/onsemi/SESD7L5-0DT5G/9087727

A Digikey tech forum page on this topic includes this:

However, I don’t think this configuration will work for a PU pin, because the ground diode points directly to the pin.

Attached you will see my sketch of a MCU having a Pull-up pin (PU), connected in series with a 100 Ohm resister to a periodic switch to ground. I want to provide ElectroStatic Discharge (ESD) protection.

  1. Please confirm the sketch diodes are correctly orientated to achieve ESD protection.
  2. If correct, please sketch how I would wire the above part to achieve ESD protection.

Feel free to call me at 406-465-3357 if you have questions. Thank you!


Drawing referenced by the customer does not appear to be attached.

Anyhow, the general idea would be as per below. Diode will conduct in either a reverse or forward direction depending on polarity of applied ESD event relative to system ground. Depending on polarity of applied ESD event, diode will clamp voltage on signal line to something slightly above its rated reverse breakdown voltage, or slightly less than zero. These voltages are likely to be somewhat outside of prescribed limits for logic ICs, so a series resistor can be used to limit the current flow through the IC due to these residual excess voltages.

Hi Rick,

I’m using a 5V MCU and the input is a MCU pull-up pin. For your sketch, what should be the resistor value? 100Ohm, 10Ohm?

ESD is a new area for me and I’m not sure about how the diodes are really working. What do you think about the attached sketch for more robust MCU pin protection?

The ground to the left of the switch is the same ground as the Vss in the circuit, but this is a long way from the MCU. I need industrial quality ESD protection.



Internal to the MCU, one would likely find diodes to the supply rails similar to that shown above; these on-chip protections are tiny and really only suitable for protection during handling and assembly in a mild environment, not real-world exposure.

ESD is modeled as a discharge of a small, high-voltage capacitor into the line in question. It’s a fast phenomenon, meaning that parasitic elements arising from how the circuit is constructed physically can make a difference too.


Personally, I’d be inclined to move the resistance downstream of the steering diode array; they have fine internal features, and can be damaged too. I’d look to add a placement of something in the 100-1K range that’s already on the BoM. Main thing is that it has to work with whatever pull-up resistance value one has available.

I’d aim to place the steering array outward, near the assembly envelope with a low-impedance local path to a decoupling capacitance, that connects to Vcc via whatever lengthy, circuitous route is convenient. Note that the “ground” lead extending to the contact is every bit as much a path into the system as any other wire; it may not be a bad idea to run that lead through some sort of impedance as well before connecting to the distribution point. from which the MCU etc. is supplied.

In any event, signal frequency is sorta the distinguishing factor between typical I/O signals and ESD events. The typical strategy is to create a defense in depth to the extent feasible, placing things that can redirect or dissipate the ESD charge as far out toward the assembly envelope as possible, and putting impedance between that point and the inner area where all the sensitive stuff lives in order to reduce the amount that can seep through.

At days’ end, a person has to establish expectations for what must be tolerable, and the solution also has to be functional under normal conditions. If one picks the problem apart and applies the concept that components aren’t to be stressed beyond their maximum ratings, things can make sense pretty quickly.

Thanks Rick! Just a few follow up questions:

What size capacitor would you suggest I use?

On the bottom ground line your sketch has a box “L? R?”, what is the meaning here?

Thanks again!

I’d suggest a capacitor that could absorb the charge deposited on it by the ESD event without being damaged or permitting the supply line to rise in voltage above permitted maximums. There are standard models used for testing which describe a capacitance charged to some voltage; picking the spec you want to meet and sizing a capacitance based on the capacitor charge equation (Q=C*V) would be a reasonable way to go about the matter.

The box with the question marks represents the referenced “some sort of impedance.” Inductive, resistive, whatever floats your boat and doesn’t hinder normal operation.