Custom board using Octavo Systems OSD3358-BAS and two Microchip LAN8710 ethernet PHYs. The PHYs are wired RMII which requires a 50Mhz refclk. My board design has one 50Mhz oscillator per PHY. I was having trouble with what looked like two clock signals running on top of each other. I decided to remove PHY-2’s oscillator to see if it was interfering somehow with PHY-1’s refclk. To my surprise I found was that PHY-2 still a 50Mhz refclk and it was stable. Checking PHY-1 refclk still has interference from somewhere. I removed PHY-2’s external oscillator. Again to my surprise now PHY-1 has a stable 50Mhz clock.
I have read the data sheets on the LAN 8710 and they don’t generate the refclk signal. The TI AM335x technical reference states that it doesn’t generate the 50Mhz refclk.
I have noticed that I can abort u-boot. While u-boot is aborted then the 50Mhz clock signals are not present.
Allowing u-boot to continue and sometime during kernel (4.19.106-bone49) boot the 50Mhz clock comes on for approx 180ms, stays off for approx 9 seconds and then comes back on and stays on. When the clock comes back on then the PHY link is established, the board requests and gets and IP address and eno1 is ready for use.
I think during the 180ms time, the kernel is in the process of probing the PHYs. I can only guess that something in the kernel is turning on the 50Mhz clock. What I don’t know is what is generating the 50Mhz clock and where in the kernel code the clock is controlled.
If the OSD3358 is generating the 50Mhz clock, then what internal clock is doing that?
What kernel .c code controls the clock on/off?
Is there a chapter/section in the TI AM335x technical reference manual that described what is happening?