Hi,
Custom board using Octavo Systems OSD3358-BAS and two Microchip LAN8710 ethernet PHYs. The PHYs are wired RMII which requires a 50Mhz refclk. My board design has one 50Mhz oscillator per PHY. I was having trouble with what looked like two clock signals running on top of each other. I decided to remove PHY-2’s oscillator to see if it was interfering somehow with PHY-1’s refclk. To my surprise I found was that PHY-2 still a 50Mhz refclk and it was stable. Checking PHY-1 refclk still has interference from somewhere. I removed PHY-2’s external oscillator. Again to my surprise now PHY-1 has a stable 50Mhz clock.
I have read the data sheets on the LAN 8710 and they don’t generate the refclk signal. The TI AM335x technical reference states that it doesn’t generate the 50Mhz refclk.
I have noticed that I can abort u-boot. While u-boot is aborted then the 50Mhz clock signals are not present.
Allowing u-boot to continue and sometime during kernel (4.19.106-bone49) boot the 50Mhz clock comes on for approx 180ms, stays off for approx 9 seconds and then comes back on and stays on. When the clock comes back on then the PHY link is established, the board requests and gets and IP address and eno1 is ready for use.
I think during the 180ms time, the kernel is in the process of probing the PHYs. I can only guess that something in the kernel is turning on the 50Mhz clock. What I don’t know is what is generating the 50Mhz clock and where in the kernel code the clock is controlled.
If the OSD3358 is generating the 50Mhz clock, then what internal clock is doing that?
What kernel .c code controls the clock on/off?
Is there a chapter/section in the TI AM335x technical reference manual that described what is happening?
Thank you
You can dump all the clocks with:
cat /sys/kernel/debug/clk/clk_summary
If you don’t have that…
debian@bbb-pwr03-ser11:~$ cat /etc/fstab | grep debug
debugfs /sys/kernel/debug debugfs mode=755,uid=root,gid=gpio,defaults 0 0
I’m thinking it’s these guys in your case:
debian@bbb-pwr03-ser11:~$ cat /sys/kernel/debug/clk/clk_summary | grep cpsw
cpsw_cpts_rft_clk 1 1 0 250000000 0 0 50000
cpsw_125mhz_gclk 2 3 0 125000000 0 0 50000
Regards,
Hi all,
I want to follow up on my post.
I have built two identical custom boards except for,
Board-1 (B1) does not have external 50Mhz oscillators.
Board-2 (B2) does have external 50Mhz oscillators.
I will not be using Ethernet ports in u-boot. I will be using Ethernet ports after the kernel loads in the rootfs.
U-boot board.c and mux.c have been modified to match my custom board which includes dual LAN8710 both wired as RMII.
Custom device tree (for the kernel) created to match my custom board.
B2 (oscillators installed). I don’t want the AM3358 to generate to 50Mhz refclk so I configured the gmii_sel register in the board.c file to
puts("eth0: eth1: RMII MODE\n");
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 0;
cpsw_slaves[1].phy_addr = 1;
I added this section to my custom device tree file.
&phy_sel {
// this disables the kernel from outputting the 50Mhz refclk
rmii-clock-ext;
};
The PHYs link upon applying power to the board.
B1 (no oscillator). I want the AM3358 to generate the 50Mhz refclk so I configured the gmii_sel register in the board.c file to
puts("eth0: eth1: RMII MODE\n");
writel(RMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 0;
cpsw_slaves[1].phy_addr = 1;
I did not add the phy_sel section to my custom device tree file. (Well I actually just commented it out)
The PHYs will not link until the kernel loads and turns on the 50Mhz refclk but that is good enough for my application.
Thank you,
