The Panasonic Electric Works’ Grid Eye is a thermopile-type infrared sensor with digital communication. Using advanced MEMS technology, the Grid Eye monitors the quantity of infrared rays for 64 pixels of data. This page describes the internal memory structure that can be accessed through an I2C interface. This information was sourced from the GridEYE datasheet.
I2C Slave Address
There are two I2C addresses available for the Grid Eye. The Grid Eye address can be selected by connecting the AD_SELECT terminal to GND or with a 10k Ω pull-up resistor to VDD.
| AD_Select Connection | I2C Address |
|---|---|
| GND | 0b1101000 |
| Pull-up to VDD | 0b1101001 |
Power Control Register
The Grid Eye has four modes of operation. The operations include normal, sleep, and two types of stand-by. These modes can be selected by writing to this register. The current mode of operation can also be read from this register. This register is at address 0x00.
| Bits | Result |
|---|---|
| 0b00000000 | Normal Mode |
| 0b00010000 | Sleep Mode |
| 0b00100000 | Stand-by with 60 second interference |
| 0b00100001 | Stand-by with 10 second interference |
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x00 | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Reset Register
The Reset Register is used for two operations: full software reset and flag reset. This register is write-only and a full byte wide starting at address 0x01.
| Bits | Result |
|---|---|
| 0b00110000 | Flag Reset |
| 0b00111111 | Software Reset |
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x01 | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
Frame Rate
The frame rate of the Grid Eye can be set and read from the register at address 0x02. The ability to select between 1 FPS and 10 FPS are available. The default value is 10 frames per second.
| Bit 0 | Result |
|---|---|
| 0 | 10 FPS (default) |
| 1 | 1 FPS |
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x02 | - | - | - | - | - | - | - | Bit 0 |
Interrupt Setup
Interrupts can be setup internally inside of the Grid Eye. When a single pixel passes a given value, an interrupt will occur. When an interrupt occurs, the interrupt flag in the Status Register is set high. Additionally, the INT pin of the Grid Eye can be setup to be pulled low when an interrupt occurs. This register is both readable and writable and is at address 0x03. See the Interrupt Level Register to set the trip values for the interrupt.
| Bit 0 | Result |
|---|---|
| 0 | INT Pin reactive (High Impedance) (default) |
| 1 | INT Pin Enable |
| Bit 1 | Result |
|---|---|
| 0 | Difference Mode (default) |
| 1 | Absolute Mode |
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x03 | - | - | - | - | - | - | Bit 1 | Bit 0 |
Status Register
The Status Register contains flags on the thermistor temperature output overflow, temperature output overflow, and pixel interrupt. The address for the Status Register is 0x04. The flags can be reset by writing to the Status Clear Register.
| Bit 1 | Result |
|---|---|
| 0 | No Interrupt |
| 1 | Interrupt Occurred |
| Bit 2 | Result |
|---|---|
| 0 | Temperature Output OK |
| 1 | Temperature Output Overflow |
| Bit 3 | Result |
|---|---|
| 0 | Thermistor Temperature OK |
| 1 | Thermistor Temperature Overflow |
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x04 | - | - | - | - | Bit 3 | Bit 2 | Bit 1 | - |
Status Clear Register
The flags in the Status Register can be reset by writing to the Status Clear Register. This register is designed to only be written to. After writes occur to this register, the value of each flag reset bit is set to zero.
| Bit 1 | Result |
|---|---|
| 0 | Don’t Reset Interrupt Flag |
| 1 | Reset Interrupt Flag |
| Bit 2 | Result |
|---|---|
| 0 | Don’t Reset Temperature Output Overflow Flag |
| 1 | Reset Temperature Output Overflow Flag |
| Bit 3 | Result |
|---|---|
| 0 | Don’t Reset Thermistor Temperature Flag |
| 1 | Reset Thermistor Temperature Overflow Flag |
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x05 | - | - | - | - | Bit 3 | Bit 2 | Bit 1 | - |
Average Register
This register is used for the moving average output. This register is currently known to be read-only although some documentation shows this register as writable.
| Bit 5 | Result |
|---|---|
| 1 | Twice moving average |
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x07 | - | - | Bit 5 | - | - | - | - | - |
Interrupt Level Register
This register sets the interrupt trip values. Both lower limit, upper limit, and the hysteresis level can be set and read between the addresses 0x08 to 0x0D. Interrupt level setting is done using two’s complement. Initially the register is filled with zeroes.
| Address | Function | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| 0x08 | Upper Limit | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0x09 | Upper Limit | - | - | - | - | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
| 0x0A | Lower Limit | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0x0B | Lower Limit | - | - | - | - | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
| 0x0C | Hysteresis Level | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0x0D | Hysteresis Level | - | - | - | - | Bit 11 | Bit 10 | Bit 9 | Bit 8 |
Thermistor
Thermistor data is stored in addresses 0x0E and 0x0F. This value is the temperature as seen on the Grid Eye module. This value is very useful in filtering out background noise from the raw pixel values. The resolution of the thermistor data is 0.0625°C. This register is read-only.
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x0E | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0x0F | - | - | - | - | + / - | Bit 10 | Bit 9 | Bit 8 |
Interrupt Table Register
When an interrupt occurs due to the pixel temperature, the pixel that caused the interrupt is flagged in this register.
| Bit | Result |
|---|---|
| 0 | Flag was not set |
| 1 | Flag was set for this pixel |
| Address | ||||||||
|---|---|---|---|---|---|---|---|---|
| 0x10 | Pix 7 | Pix 6 | Pix 5 | Pix 4 | Pix 3 | Pix 2 | Pix 1 | Pix 0 |
| 0x11 | Pix 15 | Pix 4 | Pix 13 | Pix 12 | Pix 11 | Pix 10 | Pix 9 | Pix 8 |
| 0x12 | Pix 23 | Pix 22 | Pix 21 | Pix 20 | Pix 19 | Pix 18 | Pix 17 | Pix 16 |
| 0x13 | Pix 31 | Pix 30 | Pix 29 | Pix 28 | Pix 27 | Pix 26 | Pix 25 | Pix 24 |
| 0x14 | Pix 39 | Pix 38 | Pix 37 | Pix 36 | Pix 35 | Pix 34 | Pix 33 | Pix 32 |
| 0x15 | Pix 47 | Pix 46 | Pix 45 | Pix 44 | Pix 43 | Pix 42 | Pix 41 | Pix 40 |
| 0x16 | Pix 55 | Pix 54 | Pix 53 | Pix 52 | Pix 51 | Pix 50 | Pix 49 | Pix 48 |
| 0x17 | Pix 63 | Pix 62 | Pix 61 | Pix 60 | Pix 59 | Pix 58 | Pix 57 | Pix 56 |
Pixel Data
The raw values are stored in the Grid Eye register starting at address 0x80 and continuing through bit 0xFF. The data can only be read. When updating, the Grid Eye updates all of the pixel data at once. This prevents any stale data from being collected during a read.
| Address | Pixel # | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| Pixel 0 | 0x80 | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Pixel 0 | 0x81 | - | - | - | - | + / - | Bit 10 | Bit 9 | Bit 8 |
| … | … | … | … | … | … | … | … | … | … |
| Pixel 63 | 0xFE | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 0xFF | - | - | - | - | + / - | Bit 10 | Bit 9 | Bit 8 |
The following shows how the pixels are identified within the Grid Eye.
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
| 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
| 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 |
| 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
| 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
| 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 |
| 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 |
Full Register Map
| Address | Read/Write | Description |
|---|---|---|
| 0x00 | R/W | Operating Mode |
| 0x01 | W | Software Reset |
| 0x02 | R/W | Frame Rate |
| 0x03 | R/W | Interrupt Function |
| 0x04 | R | Interrupt Flag |
| 0x05 | W | Interrupt Flag Clear |
| 0x06 | - | - |
| 0x07 | R | Moving Average Output Mode |
| 0x08 | R/W | Upper Interrupt Value |
| 0x09 | R/W | Upper Interrupt Value |
| 0x0A | R/W | Lower Interrupt Value |
| 0x0B | R/W | Lower Interrupt Value |
| 0x0C | R/W | Hysteresis Interrupt Value |
| 0x0D | R/W | Hysteresis Interrupt Value |
| 0x0E | R | Thermistor Output Value |
| 0x0F | R | Thermistor Output Value |
| 0x10 | R | Pixel 0-7 Interrupt Flag |
| 0x11 | R | Pixel 8-15 Interrupt Flag |
| 0x12 | R | Pixel 16-23 Interrupt Flag |
| 0x13 | R | Pixel 24-31 Interrupt Flag |
| 0x14 | R | Pixel 32-39 Interrupt Flag |
| 0x15 | R | Pixel 40-47 Interrupt Flag |
| 0x16 | R | Pixel 48-55 Interrupt Flag |
| 0x17 | R | Pixel 56-63 Interrupt Flag |
| 0x18 | - | - |
| … | - | - |
| 0x7F | - | - |
| 0x80 | R | Pixel 0 Output Value (low) |
| 0x81 | R | Pixel 0 Output Value (high) |
| 0x82 | R | Pixel 1 Output Value (low) |
| 0x83 | R | Pixel 1 Output Value (high) |
| 0x84 | R | Pixel 2 Output Value (low) |
| 0x85 | R | Pixel 2 Output Value (high) |
| 0x86 | R | Pixel 3 Output Value (low) |
| 0x87 | R | Pixel 3 Output Value (high) |
| 0x88 | R | Pixel 4 Output Value (low) |
| 0x89 | R | Pixel 4 Output Value (high) |
| 0x8A | R | Pixel 5 Output Value (low) |
| 0x8B | R | Pixel 5 Output Value (high) |
| 0x8C | R | Pixel 6 Output Value (low) |
| 0x8D | R | Pixel 6 Output Value (high) |
| 0x8E | R | Pixel 7 Output Value (low) |
| 0x8F | R | Pixel 7 Output Value (high) |
| 0x90 | R | Pixel 8 Output Value (low) |
| 0x91 | R | Pixel 8 Output Value (high) |
| 0x92 | R | Pixel 9 Output Value (low) |
| 0x93 | R | Pixel 9 Output Value (high) |
| 0x94 | R | Pixel 10 Output Value (low) |
| 0x95 | R | Pixel 10 Output Value (high) |
| 0x96 | R | Pixel 11 Output Value (low) |
| 0x97 | R | Pixel 11 Output Value (high) |
| 0x98 | R | Pixel 12 Output Value (low) |
| 0x99 | R | Pixel 12 Output Value (high) |
| 0x9A | R | Pixel 13 Output Value (low) |
| 0x9B | R | Pixel 13 Output Value (high) |
| 0x9C | R | Pixel 14 Output Value (low) |
| 0x9D | R | Pixel 14 Output Value (high) |
| 0x9E | R | Pixel 15 Output Value (low) |
| 0x9F | R | Pixel 15 Output Value (high) |
| 0xA0 | R | Pixel 16 Output Value (low) |
| 0xA1 | R | Pixel 16 Output Value (high) |
| 0xA2 | R | Pixel 17 Output Value (low) |
| 0xA3 | R | Pixel 17 Output Value (high) |
| 0xA4 | R | Pixel 18 Output Value (low) |
| 0xA5 | R | Pixel 18 Output Value (high) |
| 0xA6 | R | Pixel 19 Output Value (low) |
| 0xA7 | R | Pixel 19 Output Value (high) |
| 0xA8 | R | Pixel 20 Output Value (low) |
| 0xA9 | R | Pixel 20 Output Value (high) |
| 0xAA | R | Pixel 21 Output Value (low) |
| 0xAB | R | Pixel 21 Output Value (high) |
| 0xAC | R | Pixel 22 Output Value (low) |
| 0xAD | R | Pixel 22 Output Value (high) |
| 0xAE | R | Pixel 23 Output Value (low) |
| 0xAF | R | Pixel 23 Output Value (high) |
| 0xB0 | R | Pixel 24 Output Value (low) |
| 0xB1 | R | Pixel 24 Output Value (high) |
| 0xB2 | R | Pixel 25 Output Value (low) |
| 0xB3 | R | Pixel 25 Output Value (high) |
| 0xB4 | R | Pixel 26 Output Value (low) |
| 0xB5 | R | Pixel 26 Output Value (high) |
| 0xB6 | R | Pixel 27 Output Value (low) |
| 0xB7 | R | Pixel 27 Output Value (high) |
| 0xB8 | R | Pixel 28 Output Value (low) |
| 0xB9 | R | Pixel 28 Output Value (high) |
| 0xBA | R | Pixel 29 Output Value (low) |
| 0xBB | R | Pixel 29 Output Value (high) |
| 0xBC | R | Pixel 30 Output Value (low) |
| 0xBD | R | Pixel 30 Output Value (high) |
| 0xBE | R | Pixel 31 Output Value (low) |
| 0xBF | R | Pixel 31 Output Value (high) |
| 0xC0 | R | Pixel 32 Output Value (low) |
| 0xC1 | R | Pixel 32 Output Value (high) |
| 0xC2 | R | Pixel 33 Output Value (low) |
| 0xC3 | R | Pixel 33 Output Value (high) |
| 0xC4 | R | Pixel 34 Output Value (low) |
| 0xC5 | R | Pixel 34 Output Value (high) |
| 0xC6 | R | Pixel 35 Output Value (low) |
| 0xC7 | R | Pixel 35 Output Value (high) |
| 0xC8 | R | Pixel 36 Output Value (low) |
| 0xC9 | R | Pixel 36 Output Value (high) |
| 0xCA | R | Pixel 37 Output Value (low) |
| 0xCB | R | Pixel 37 Output Value (high) |
| 0xCC | R | Pixel 38 Output Value (low) |
| 0xCD | R | Pixel 38 Output Value (high) |
| 0xCE | R | Pixel 39 Output Value (low) |
| 0xCF | R | Pixel 39 Output Value (high) |
| 0xD0 | R | Pixel 40 Output Value (low) |
| 0xD1 | R | Pixel 40 Output Value (high) |
| 0xD2 | R | Pixel 41 Output Value (low) |
| 0xD3 | R | Pixel 41 Output Value (high) |
| 0xD4 | R | Pixel 42 Output Value (low) |
| 0xD5 | R | Pixel 42 Output Value (high) |
| 0xD6 | R | Pixel 43 Output Value (low) |
| 0xD7 | R | Pixel 43 Output Value (high) |
| 0xD8 | R | Pixel 44 Output Value (low) |
| 0xD9 | R | Pixel 44 Output Value (high) |
| 0xDA | R | Pixel 45 Output Value (low) |
| 0xDB | R | Pixel 45 Output Value (high) |
| 0xDC | R | Pixel 46 Output Value (low) |
| 0xDD | R | Pixel 46 Output Value (high) |
| 0xDE | R | Pixel 47 Output Value (low) |
| 0xDF | R | Pixel 47 Output Value (high) |
| 0xE0 | R | Pixel 48 Output Value (low) |
| 0xE1 | R | Pixel 48 Output Value (high) |
| 0xE2 | R | Pixel 49 Output Value (low) |
| 0xE3 | R | Pixel 49 Output Value (high) |
| 0xE4 | R | Pixel 50 Output Value (low) |
| 0xE5 | R | Pixel 50 Output Value (high) |
| 0xE6 | R | Pixel 51 Output Value (low) |
| 0xE7 | R | Pixel 51 Output Value (high) |
| 0xE8 | R | Pixel 52 Output Value (low) |
| 0xE9 | R | Pixel 52 Output Value (high) |
| 0xEA | R | Pixel 53 Output Value (low) |
| 0xEB | R | Pixel 53 Output Value (high) |
| 0xEC | R | Pixel 54 Output Value (low) |
| 0xED | R | Pixel 54 Output Value (high) |
| 0xEE | R | Pixel 55 Output Value (low) |
| 0xEF | R | Pixel 55 Output Value (high) |
| 0xF0 | R | Pixel 56 Output Value (low) |
| 0xF1 | R | Pixel 56 Output Value (high) |
| 0xF2 | R | Pixel 57 Output Value (low) |
| 0xF3 | R | Pixel 57 Output Value (high) |
| 0xF4 | R | Pixel 58 Output Value (low) |
| 0xF5 | R | Pixel 58 Output Value (high) |
| 0xF6 | R | Pixel 59 Output Value (low) |
| 0xF7 | R | Pixel 59 Output Value (high) |
| 0xF8 | R | Pixel 60 Output Value (low) |
| 0xF9 | R | Pixel 60 Output Value (high) |
| 0xFA | R | Pixel 61 Output Value (low) |
| 0xFB | R | Pixel 61 Output Value (high) |
| 0xFC | R | Pixel 62 Output Value (low) |
| 0xFD | R | Pixel 62 Output Value (high) |
| 0xFE | R | Pixel 63 Output Value (low) |
| 0xFF | R | Pixel 63 Output Value (high) |
Relevant Products
| Panasonic Electric Works Part Number | Digi-Key Part Number | Packaging | Description | |
|---|---|---|---|---|
| AMG8831 | 255-3509-2-ND | Tape & Reel | Grid-EYE, 3.3 V, High gain | |
| 255-3509-1-ND | Cut Tape | |||
| 255-3509-6-ND | Digi-Reel® | |||
| AMG8832 | 255-3506-2-ND | Tape & Reel | Grid-EYE, 3.3 V, Low gain | |
| 255-3506-1-ND | Cut Tape | |||
| 255-3506-6-ND | Digi-Reel® | |||
| AMG8851 | 255-3507-2-ND | Tape & Reel | Grid-EYE, 5.0 V, High gain | |
| 255-3507-1-ND | Cut Tape | |||
| 255-3507-6-ND | Digi-Reel® | |||
| AMG8852 | 255-3508-2-ND | Tape & Reel | Grid-EYE, 5.0 V, Low gain | |
| 255-3508-1-ND | Cut Tape | |||
| 255-3508-6-ND | Digi-Reel® |