DE0-nano-SoC: Accessing FPGA implemented registers

Hello, I am trying to do what many people did before albeit possibly in a different environment. I have a running Debian on my DE0 (Thanks @RobertCNelson !) https://www.digikey.com/eewiki/display/linuxonarm/DE0-Nano-SoC+Kit
I can load FPGA portion with a simple project through Quartus programmer or load the rbf file through uboot. So far so good. However, last (uncounted) days I struggled with attempts to access registers implemented in Platform Designer as “PIO Intel FPGA IP” (Avalon Memory Mapped Slave).
I can compile a C code natively and mmap:

h2f_lw_axi_master = mmap(NULL, h2f_lw_axi_master_span, PROT_READ | PROT_WRITE, MAP_SHARED, fd_dev_mem, h2f_lw_axi_master_ofst);
where
h2f_lw_axi_master_ofst = 0xff200000
h2f_lw_axi_master_span = 0x00200000

However, an attempt to read or write results in Bus error.
Now I would like to know “what tree to bark at”:

sudo cat /proc/iomem
00000000-3fffffff : System RAM
00008000-00afffff : Kernel code
00c00000-00d0939f : Kernel data
ff702000-ff703fff : /soc/ethernet@ff702000
ff704000-ff704fff : /soc/dwmmc0@ff704000
ff706000-ff706fff : /soc/fpgamgr@ff706000
ff708000-ff708fff : /soc/gpio@ff708000
ff709000-ff709fff : /soc/gpio@ff709000
ff70a000-ff70afff : /soc/gpio@ff70a000
ffb40000-ffb4fffe : /soc/usb@ffb40000
ffb90000-ffb90003 : /soc/fpgamgr@ff706000
ffc02000-ffc0201f : serial
ffc03000-ffc0301f : serial
ffc04000-ffc04fff : /soc/i2c@ffc04000
ffc05000-ffc05fff : /soc/i2c@ffc05000
ffd02000-ffd02fff : /soc/watchdog@ffd02000
ffd05000-ffd05fff : rstmgr
ffe01000-ffe01fff : /soc/amba/pdma@ffe01000
ffe01000-ffe01fff : /soc/amba/pdma@ffe01000
ffff0000-ffffffff : ffff0000.sram

The LWFPGASLAVES address region (0xFF200000) does not seem to be listed above.
Do I need to implement Device Tree Overlay (tried and kept failing) or do I need to enable the existing driver in some way? Or could the Bus error culprit actually be the FPGA image not implementing a register at the intended address?
I tried accessing GPIO0 register of the HPS and got Seg fault. Good to know I am doing something, right? I suppose the register is in use by some driver (like the LED driver?)
Could anyone please point me to a cohesive set of examples to give me a starting point? Many of the projects I found as a reference are using different kernel and different vintage of tools and it is quite possibly part of my confusion. I would prefer staying with the OS build as per the link above (kernel 4.14.130-ltsi-socfpga-r2) and get a pointer to any simple Linux program accessing a register or pair and corresponding FPGA project.
I may try to follow the https://github.com/sahandKashani/SoC-FPGA-Design-Guide/tree/master/DE0_Nano_SoC in its entirety. (This is where I borrowed the qsys project from). But that may mean starting over with different Linux build. And perhaps I am just missing something simple?
Thanks!

Hi @mates, sorry for the lateness over the Holiday! :wink:

Just implement it into your device tree, no reason to add overlays to the fun… This can be missing clock source, or kernel premissions.

Sadly, I never did too much on the FPGA side with this board. As I was mostly interested in the Cortex-A9 at the time.

Probably the best place to see how this would work, would be to look at the “MiSTer” project on github:

They utilize the Altera/DE0_Nano_Soc with the 4.19.x branch of the kernel. They’ve implemented a ton of emulation targets on the FGPA layer sharing sound/graphics/input/etc with the ARM core. :wink:

Regards,

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