Discover the functions of open drain and open collector circuits

There is a popular post here on the DigiKey TechForum that explores the “what” aspects of an open drain configuration. The post presents the open-drain concept as a digital circuit that requires an external pull-up resistor. That is a good answer, but we should expand our knowledge by asking “why” an open drain circuit is desirable.

Before we start, let’s make a running list of logic devices that feature either the open drain or open collector connections:

  • 74 series logic:7401, 7403, 7405, (7406 and higher current 7416), (7407 and higher current 7417), and a dozen more family members

  • 4000 series logic devices such as the 40107

  • comparators such as the LM339D

  • nearly all Inter-Integrated Circuit (I^2C) including the sensor you recently connected to your microcontroller including the new Adafruit STEMMA QT and Sparkfun Qwiic interfaces.

  • Dallas 1-wire devices such as the DS18B20+ temperature sensor

  • Microcontrollers including new PIC family members such as the PIC16F18026. It features configurable open-drain connections for each I/O pin.

Many related examples could be found. However, the point has been made; digital devices with open drain and open collector outputs are common. It is helpful to know more about how this technology and why it is so advantageous. In this post we will explore why this 50 plus year old configuration remains relevant and why it is a design feature in modern components such as the PIC, Stemma QT, and Qwiic.

For clarity and brevity, the term open drain will be used for the remainder of this post.

Tech Tip: There are good reasons for using the open drain configuration. Speed is not one of those reasons. The sluggishness typically associated with the low to high transition will be address in another article.

Level Shifting with Open Drain Devices

The open drain connections may be used for level shifting. As many of you have experienced, there was a time when 5 VDC digital logic was common. A prime example is the Arduino UNO with its 5 VDC I/O. However, in recent years, the 3.3 VDC has become increasingly popular. Today, it’s not uncommon to encounter microcontroller, FPGA, and sensors to be physically connected in a system featuring multiple voltages. I’m sure you have encountered the “5 VDC tolerant” specification on a variety of components. You may have also seen level shifting circuits.

The open drain configuration easily facilitates level shifting between the various voltage. An example is shown as the fictitious MiltiSim Live simulation presented in Figure 1. Here we see a pair of logic buffers driving MOSFETs. Each MOSFET drives an incandescent lamp which serves as a stand in for the obligatory pull up resistor. Note that one lamp is connected to a 3.3 VDC source while the other is connected to a 5.0 VDC source. In this example the MOSFET serves to isolate the driving digital logic from the external voltage. Another way of saying this is that all power supplies share a common ground but there is no interaction between the positive voltages. One final note, the incandescent lamp glows when current flow in the circuit. This is a good visual indicator but can be misleading as the lamp is active logic low while most people thing in terms of positive high logic.

Figure 1: Representative schematic for level shifting between 3.3 and 5.0 VDC.

Figure 1: Representative schematic for level shifting between 3.3 and 5.0 VDC.

Regarding Multisim Live: If you click on the photo in this post, you will be led to a publicly available simulation of the circuit. Everyone can run the simulation using the various controls. However, you may not modify the circuit unless you have a Multisim Live subscription. Multisim Live is an online service hosted by Digilent which is a National Instruments company.]

We can relate Figure 1 back to the PIC microcontroller. In this example, let’s assume the PIC is driven by a 5.0 VDC source. Let the I/O be configured for open drain. The PIC now has the same configuration as Figure 1. Here, the PIC’s internal logic uses the 5 VDC rail. The PIC’s MOS driver is referenced to ground in the same way as the 2N7000G MOSFET in Figure 1. The incandescent lamps may be replaced with pull-up resistors allowing the PIC to function in a mixed voltage system with the ability to drive and accept inputs from external 3.3 and 5.0 VDC devices.

Tech Tip: A pair of clamp diodes are included on every microcontroller I/O pin. These diodes provide a small measure of overvoltage and electrostatic protection. The level shifting described in this note works when a microcontroller powered by 5.0 VDC is used to drive a 3.3 and 5.0 VDC logic via the open drain connections. However, this will not work in reverse. We risk damaging the microcontroller supplied by 3.3 VDC when a 5.0 VDC load is applied via the open drain connection. The associated I/O pin-to-VDD diode will be forward biased thereby limiting the pin voltage to 3.3 VDC plus one diode drop. Without appropriate current limiting the microcontroller will be destroyed. This isn’t a significant problem as an external MOSFET such as the 2N7000 may be driven by the PIC using a series resistor.

Wired NOR with Open Drain Devices

In the first part of this post, we showed how an open-drain configuration may be used for level shifting. We will now explore how several open drain devices may be connected to form a shared bus. This bus is a central feature of the I^2C transaction. Recall that the I^2C interface allows multiple nodes to share data on a single two-wire bus. The Serial Data (SDA) and the Serial Clock (SCL) lines each include a pull up resistor similar to the representation included as Figure 2.

Tech Tip: The I^2C communications bus is most effective when several devices need to share a small amount of data. The related SPI protocol is preferred when a single device must share a large amount of data. SPI is faster a as a dedicated line is used to select the desired device thus eliminating the need to send the address over the serial interface. SPI allows full duplex. Finally, SPI uses crisp MOS drivers for the data lines. It does not suffer the sluggish response associated with the I^2C pull up resistors; a topic to be covered in another installment.

Figure 2: Schematic for wired NOR featuring open drain devices.

Figure 2: Schematic for wired NOR featuring open drain devices.

Figure 2 shows three open drain MOSFETS. The drains are connected to a common pull up resistor. In this example, a light bulb serves as the pull-up resistor allow us to visualize the flow of current. Notice that the logic OR nature of the circuit. The bulb will light when a single MOSFET or a combination of MOSFETS are activated. The bulb will be extinguished when all MOSFETs are turned off.

Independence and isolation are important considerations for Figure 2. The only stipulation is that all devices share a common ground. Each MOSFET will act against the pull-up resistor pulling it toward the shared ground. At this point we can shift focus to the I^2C communication bus as show in the Figure 3.

Tech Tip: The terms “logic high” and “logic low” can be confusing to the digital electronics novice. Consider the Figure 2. From the perspective of the lightbulb (logic low) the circuit is wired OR: the bulb will light when any of the logic inputs is asserted. However, when we consider the logic high perspective, the circuit is more appropriately called a wired NOR. The output is high if, and only if, all inputs are turned off.

I2C Communication Bus with Open Drain Devices

Figure 3 presents a microcontroller system, collection of sensors, and an actuator appropriate for monitoring and automated care of a house plant. All the open drain concepts originally presented in Figure 2 are retained. The only difference is that the MOS open drain devices are hidden inside each block. The pull-up resistor and the common ground are retained. We can see that each block may communicate by pulling the SDA line. If necessary, each device may pull the clock line low. This is a process known as clock stretching which may be used by a sensor to slow down the rate of data transfer.

Figure 3: Block diagram representation of the Wired AND logic featured in the I^2C communications bus.

Conclusion

As we conclude, it’s important to recognize that a robust protocol is necessary for communication on the I^2C bus. Each device must pull on the correct resistors at the correct time. A failure will result in garbled communications as only one device may communicate at any given time. While we certainly could go on to explore the I^2C protocols, it is sufficient to conclude with the highlights of the open drain connection.

The open drain and open collector concept can be traced back half a century to the 74 series logic. At that time, designers would have appreciated the savings (reduced chip count) offered by circuits such as the wires OR. Today, the open drain configuration remains an essential design tool especially in on-board communication and some applications for level shifting.

About this author

Aaron Dahlen, LCDR USCG (Ret.), serves as an application engineer at DigiKey. He has a unique electronics and automation foundation built over a 27-year military career as a technician and engineer which was further enhanced by 12 years of teaching (interwoven). With an MSEE degree from Minnesota State University, Mankato, Dahlen has taught in an ABET-accredited EE program, served as the program coordinator for an EET program, and taught component-level repair to military electronics technicians. Dahlen has returned to his Northern Minnesota home and thoroughly enjoys researching and writing educational articles about electronics and automation.

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Dahlen is an active contributor to the DigiKey TechForum. At the time of this writing, he has created over 136 unique posts and provided an additional 461 forum posts. Dahlen shares his insights on a wide variety of topics including microcontrollers, FPGA programming in Verilog, and industrial controls.

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