ESP32-C5 Boot Failure with Shared External Clock

Support
1

Hello everyone,

We are currently developing an 8-node phase-coherent WiFi CSI (Channel State Information) channel sounder using the ESP32-C5 for academic MIMO propagation research.

To maintain phase coherence across all receiver nodes and eliminate inter-node Carrier Frequency Offset (CFO), we must share a common frequency reference. According to Espressif’s ESP-Techpedia documentation, the “esp-crab” project handles multi-antenna RF phase synchronization via a common crystal.

However, we have run into a critical hardware roadblock, and the hardware design files (schematics, BOM) for the esp-crab example are missing from Espressif’s repository [https://github.com/espressif/esp-csi/tree/master/examples/esp-crab\].

The Problem: We are attempting a master/slave clock topology, but the slave ESP32-C5 microcontrollers fail to boot when driven by the shared clock source.

Because the reference schematics are unavailable, we are flying blind regarding the specific hardware requirements for external clocking on this chip. We have also opened an issue on GitHub (Issue #259 on espressif/esp-csi) but are hoping someone in the community or the DigiKey engineering team might have experience with this.

Our specific questions are:

  • Boot Requirements: Are there specific eFuse configurations, strapping pin states, or input voltage swing requirements on XTAL_P to allow the ESP32-C5 to boot successfully without a dedicated crystal?

  • Pin Treatment: What is the proper hardware treatment of the XTAL_P and XTAL_N pins on the slave chips? (e.g., should XTAL_N be left floating, AC-coupled to GND, or actively driven?)

  • Internal Oscillator: How does the internal Pierce oscillator behave when driven externally, and does it need to be explicitly disabled to prevent startup hangs?

  • Topology: Is a dedicated clock fanout buffer strictly required to scale this reliably to an 8-node setup, or can the master drive them directly with appropriate impedance matching?

If anyone has successfully implemented a shared clock architecture on the ESP32-C5 (or similar ESP32-C series) or has insights into the undocumented boot requirements for external clocking, your guidance would be greatly appreciated. We are finalizing our custom PCB design and this is our last major hurdle.

Thank you in advance!

2

Hello matteo.schembri, welcome to the TechForum! I do appreciate the detailed description of the problem you are facing. However, this is a pretty advanced ESP32-C6 hardware/boot topic. You may have better visibility and more directed answers if you were to look through their ESP32 forum and even look at their technical inquiry page:

ESP32 Forum

Technical Inquiries

I apologize as I do not have this amount of experience to know how to approach your questions directly.

3

I’m not an expert on the subject matter, but from this source:

It states the following:

Clock Source

ESP32-C5 supports two external clock sources:

External Crystal Clock Source (Compulsory)

The ESP32-C5 firmware only supports 48 MHz crystal.

That implies that, at a minimum, that they don’t expect one to be adding an external clock source, and that it would require delving deep into the firmware to figure out how to reconfigure it to accept an external clock.