EVAL-AD1938AZ DIP Switch settings for MCLK

I am trying to setup the Evaluation board for the AD1938.
I need the AD1938 to be in direct 512xfs mode.
In the datasheet for the development board (UG-045) it states that for DIP Switch S2 position 7 can select either 256xfs or 128xfs.
Does this mean that I can’t have the eval board accept a MLCK speed above that even when it is in slave mode? Or am I just reading it wrong?

Thanks for any input.

Hello Thaines3,

Thank you for your inquiry.

I checked ADI’s EngineerZone first to see if anyone has had similar questions and didn’t find an answer to your specific question.

< Click Here for Analog Devices Inc EngineerZone content for your evaluation board >

You may find that would be a better suited venue for this kind of question.

ADI’s forum will indeed be the more likely place to find somebody with hands-on familiarity with the platform.

That said, S2 position 7 appears to relate to selection of an SPDIF clock rate, whereas “direct 512xFs mode” relates to selection of the clock source for the ADC/DAC sections. So, not the same thing. The “setting up the master clock” section in the user’s guide would be a section to read carefully, in conjunction with the relevant sections of the AD1938 datasheet. The latter tells you what provisions and possibilities are provided by the chip, while the UG describes how the eval board is built to facilitate using those options.

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