Guidance on Grounding and Trace Design for Mixed ±15V and 5V PCB

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1

I am currently designing a high-performance Electrical Impedance Tomography (EIT) device and would greatly appreciate your guidance on grounding, power distribution, and trace design. Here is a summary of the system:

Components:

  • Eight THS3091DDAR high-speed current-feedback amplifiers (Texas Instruments)

  • Four ADG1408YRUZ-REEL7 analog multiplexers (Analog Devices)

  • AD9833 sine wave generator for current injection

  • Microcontroller-based control circuitry for the multiplexers

Power Supplies:

  • Dual-rail ±15V for all THS3091DDAR and ADG1408YRUZ-REEL7 devices

  • 5V single supply for AD9833 and digital control circuits

Design Context:

  • The ±15V rails feed eight THS3091 amplifiers and four ADG1408 multiplexers, all on the same PCB layer.

  • The AD9833 generates a sine wave at 100 kHz for current injection into the EIT electrodes.

  • The system requires precise and low-noise analog measurements of the multiplexed voltage signals.

  • Multiplexers are controlled via microcontroller GPIOs, which I am considering isolating digitally using ISO isolators.

  • I plan to minimize interference and preserve signal integrity while managing dual-supply analog and digital circuits.

Technical Questions:

  1. Grounding Strategy:
    Given the mixed ±15V analog rails and 5V digital control, what is the recommended grounding approach for optimal signal integrity? Specifically:

  • Should I create separate ground polygons for each functional block (THS3091 + ADG1408 vs AD9833 + digital control)?

  • Or should I use a shared ground plane with partitioning, connecting polygons through a 0Ω resistor for controlled merging?

  • How can I minimize ground loops and prevent noise coupling into the THS3091 outputs and multiplexed analog signals in this configuration?

  1. Power Distribution and Trace Width:

  • What trace width is recommended for the ±15V rails feeding all eight THS3091DDAR and four ADG1408YRUZ-REEL7 devices to prevent voltage drops and IR loss while maintaining high-speed analog performance?

  • Are there recommended decoupling or layout practices for THS3091 and ADG1408 in a high-frequency (100 kHz) EIT application?

  1. Additional Recommendations:

  • Any advice on isolating the microcontroller control signals to the MUX without affecting analog signal integrity?

  • PCB layout best practices to ensure minimal cross-talk and optimal SNR in the voltage measurements of the EIT system.

This guidance is critical for ensuring accurate and stable EIT measurements and avoiding unwanted artifacts from power distribution or grounding issues.

2

Welcome to the forum.

I’d start by assuming that this may take multiple cycles of: board design, prototype build and system test, to get a production ready design.

If possible, I’d prototype the design without a custom PCB first, then after working out any signal integrity issues I’d create a simple clean board layout for the first PCB prototype without worrying if it will fit in the target housing. The 2nd prototype is where I’d start working on fitting into the target housing without destroying signal integrity.

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Re: question 1, a practical starting point is to implement grounding using a single, contiguous ground plane with minimal via penetrations and which is NOT deliberately carved up into sections. Depending on the design, this may expand into multiple ground planes on different layers.

The reason for this guidance is that partitioning one’s ground reference into multiple domains may sound like a good idea and might work OK on an eval board where the DUT is about the only IC present, in real designs where multiple ICs need to talk to each other such partitioning usually ends up causing signal integrity problems by forcing return-path currents to overlap, formation of parasitic antennas, and other effects.

Instead, be thoughtful in regard to component placement, recognizing that return-path currents follow the path of least impedance, not resistance. As frequencies increase and reactive components become more dominant, the tendency is for return-path currents to travel on adjacent layers, regardless of what names might be assigned in the schematic.

There are many online resources relating to this topic, some good and some not. The ones that suggest partitioning one’s ground planes tend to be of the not-good type.

Re: question 2, answers may vary depending on the copper thickness used, trace routing, expected output loading, and other factors. Compare the impedance of the supply network feeding each device against that device’s PSRR vs frequency characteristics, and add filtering/decoupling as necessary to move the intersection of the two into a territory you’re content with.

Also, for what it’s worth 100kHz isn’t a particularly high frequency in the present age. Be midful of the context into which a resource is speaking when looking for guidance; many signal integrity resources are speaking to applications concerned with signals at GHZ+ ranges, and may suggest measures that are quite excessive for signals that might be 3+ decimal places slower.

Re: question 3, isolators isolate, they don’t magically solve signal integrity problems. As far as best practices are concerned, there’s a lot of them, and they can vary with context. I’d recommend Bogatin’s Signal Integrity Simplified as a text worth reading on the topic.

The character of the entity that this EIS apparatus is to be used for isn’t mentioned, but its impedance will bear on amplifier selection. Speed comes with tradeoffs including power consumption, risk of oscillation, degraded offset and bias current characteristics among others. For the ~100kHz signals mentioned, a fast CFB amplifer such as the THS3091 would probably not be my first choice.

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