During power-up sequence, timing requirements are important: a given voltage rail must ramp up toward its nominal value within a defined window before the next rail is allowed to begin powering up.
For modern FPGAs and adaptive SoCs, the rails must ramp monotonically and reach their final voltages within a specified ramp time. For example, in XAPP1375, the voltage must reach ≥95% of its final value within a defined ramp period before the next rail in the sequence begins to ramp up.5
This approach helps ensure that the device exits the power-on reset (POR) state correctly and avoids issues caused by slow or improper rail rise behavior.
The power-good timer verifies that each supply reaches its set threshold voltage within a defined window during the power up sequence.
The ADM6840 uses a factory-trimmed power-good timer (PGT) to verify that each supply reaches its monitored threshold within the defined window. Unlike externally capacitor-programmed delays, factory-trimmed settings reduce variation caused by capacitor tolerance and leakage, helping provide consistent and repeatable sequencing timing.
Related Topics:
Why Do FPGAs Need Multirail Power Sequencing?
What Is the Difference Between a Power Sequencer and a Voltage Supervisor?
Why an 8-Channel Power Sequencer is Better Than Multiple 4-Channel Devices?
Reliable Power Up and Power Down Sequence
What Is Power-Down Sequencing and why it is as Important as Power-Up?
Applicable Part Numbers
| igiKey Part Number | Manufacturer Part Number |
|---|---|
| MAX16050ETI+TTR-ND,MAX16050ETI+TCT-ND,MAX16050ETI+TDKR-ND | MAX16050ETI+T |
| MAX16050ETI±ND | MAX16050ETI+ |
| 175-MAX16165ATPH+TTR-ND,175-MAX16165ATPH+TCT-ND,175-MAX16165ATPH+TDKR-ND | MAX16165ATPH+T |
| 505-MAX16165ATPH±ND | MAX16165ATPH+ |
| MAX16025TE±ND | MAX16025TE+ |
| MAX16025TE+TTR-ND,MAX16025TE+TCT-ND,MAX16025TE+TDKR-ND | MAX16025TE+T |
| 175-ADM6840EAWABFH+TTR-ND, 175-ADM6840EAWABFH+TCT-ND, 175-ADM6840EAWABFH+TDKR-ND | ADM6840EAWABFH+T |