This the first part in a series of articles related to a demo that will perform classical image processing in the Lattice ICE40 UltraPlus FPGA. The system that will be used is the Lattice ICE40 FPGA UltraPlus Breakout Board.
We will be using an encoded image with characters for transmission and reception over the 4 SPI interface inside a header file cup.h generated from the original RGB downscaled in resolution (to conserve memory resources) from GIMP and integrated into the C++ program in the x86 host as follows,
/* GIMP header image file format (RGB): /DigiKeyCoffeeCup/cup.h */
static unsigned int image_width = 64;
static unsigned int image_height = 64;
/* Call this macro repeatedly. After each use, the pixel data can be extracted */
#define HEADER_PIXEL(data,pixel) {\
pixel[0] = (((data[0] - 33) << 2) | ((data[1] - 33) >> 4)); \
pixel[1] = ((((data[1] - 33) & 0xF) << 4) | ((data[2] - 33) >> 2)); \
pixel[2] = ((((data[2] - 33) & 0x3) << 6) | ((data[3] - 33))); \
data += 4; \
}
static char *header_data =
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"";
for this image processing demo. Specifically it was derived from the following image,
and the actual 64x64 character encoded image (only for illustration purposes) is like this one.
In reality the original RGB image was encoded, formally speaking, using “characters” using the following macro,
#define HEADER_PIXEL(data,pixel) {\
pixel[0] = (((data[0] - 33) << 2) | ((data[1] - 33) >> 4)); \
pixel[1] = ((((data[1] - 33) & 0xF) << 4) | ((data[2] - 33) >> 2)); \
pixel[2] = ((((data[2] - 33) & 0x3) << 6) | ((data[3] - 33))); \
data += 4; \
}
So in order to recover it from this encoding scheme of “characters” performed by the macro, the reverse operation needs to be performed. Nevertheless, the “gray scale image” will be used in the pictures (derived from the GIMP RGB image exported as a .header file as an character encoded image) without loosing any accuracy of the description of these processes.
The setup used in this image processing demo is shown in the following diagram,
The application C++ program that resides on the x86 host will communicate with the internal finite state machine inside the FPGA via the 4 wire SPI interface and will coordinate different types of image processing transformations which are performed inside the FPGA and sent back to the x86 host. The first step in this demo is to send this image (generated in GIMP to be described later in the next article) to the FPGA and read it back without any type of transformation on the image itself as shown below. This is a real demo, and after implementing an image transmission via the 4 wire SPI interface and reading it back from the internal finite state machine (in this case without any modification on the image) implemented in Verilog HDL inside the FPGA. The following images illustrated in the next picture, are actual images used in this demo,
The image was sent and read back successfully in this initial demo of the image processing series in the Lattice ICE40 FPGA UltraPlus Breakout Board. In the next article in this series we will be describing how to do this in more detail and cover more image processing transformations for this image later. The Lattice ICE40 FPGA UltraPlus Breakout Board is an excellent, low cost, but powerful enough to even tackle image processing applications and is available at DigiKey.
Have a wonderful day!
This article is available in spanish here.
Este artículo está disponible en español aquí.