Esta es una series de artículos relacionados a una demonstración que realiza un procesamiento de imágen clásico en la plataforma Lattice ICE40 UltraPlus FPGA. El sistema usado en este demo es el Lattice ICE40 FPGA UltraPlus Breakout Board.
Estaremos usando una imágen codificada con caracteres para este demo. Estos caracteres se usan para comunicarse por la interfaz 4 wire SPI. La imágen fue exportada desde el programa GIMP como un archivo (header de C) en este caso cup.h generado desde la imagen original RGB reducida en resolución (para conservar memoria), y fue integrada a un programa C++ en la computadora x86 con Linux como sigue,
/* GIMP header image file format (RGB): /DigiKeyCoffeeCup/cup.h */
static unsigned int image_width = 64;
static unsigned int image_height = 64;
/* Call this macro repeatedly. After each use, the pixel data can be extracted */
#define HEADER_PIXEL(data,pixel) {\
pixel[0] = (((data[0] - 33) << 2) | ((data[1] - 33) >> 4)); \
pixel[1] = ((((data[1] - 33) & 0xF) << 4) | ((data[2] - 33) >> 2)); \
pixel[2] = ((((data[2] - 33) & 0x3) << 6) | ((data[3] - 33))); \
data += 4; \
}
static char *header_data =
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"";
para esta demonstración de procesamiento de imágines. Especificamente fue derivada de la siguiente imágen,
y la imágen actual de 64x64 de resolución codificada con caracters (solo para propósitos de ilustración) es como la siguiente,
En realidad, la imágen original RGB fue codificada, formalmente hablando, usando caracteres que representan la imágen usando el siguiente macro,
#define HEADER_PIXEL(data,pixel) {\
pixel[0] = (((data[0] - 33) << 2) | ((data[1] - 33) >> 4)); \
pixel[1] = ((((data[1] - 33) & 0xF) << 4) | ((data[2] - 33) >> 2)); \
pixel[2] = ((((data[2] - 33) & 0x3) << 6) | ((data[3] - 33))); \
data += 4; \
}
Para recobrar la imágen original en este esquema de codificación de caracteres realizado por el
macro, la operación en reversa se usa para ontener la imágen original. No obstante, la imágen el escala de grises se usa en estos artículos (derivado de la imágen GIMP RGB exportado como archivo header) sin perder la descripción real de estos procesos.
El siguiente esquema fue usado en este demo de procesamiento de imágenes. El mismo está ilustrado en el siguiente diagrama,
La aplicación en C++ que reside en la computadora x86 se comunica con la máquina de estados finitos interna en el FPGA via el interfaz 4 wire SPI y coordina los diferentes tipos de procesamiento de imágenes y las transformaciones que se realizan dentro del FPGA y luego enviadas hacia la computadora x86. El primer paso de este demo es enviar esta imagen (generada por GIMP descrita en el próximo artículo) a el FPGA y se lee sin ningun tipo de transformación en la imagen mostrada luego. Esto es un demo real, y luego de implementar la transmisión via el interfaz 4 wire SPI y leyendola de la máquina de estados finitos interna (en este caso sin niguna modificación de la imagen) implementada en Verilog HDL dentro del FPGA. Las siguientes imágenes ilustradas en la próxima ilustración, son las que están actualmente en el demo,
La imagen fue enviada y leida exitosamente en este demo inicial de de la serie procesamiento de imágenes en la plataforma Lattice ICE40 FPGA UltraPlus Breakout Board. En el próximo artículo de esta series, se estará describiendo mas detalles de como realizar mas transformadas a esta imagen luego. La plataforma Lattice ICE40 FPGA UltraPlus Breakout Board es una excelente, de bajo costo, pero sumamente poderosa para realizar hasta procesamiento de imágenes y está disponible en DigiKey.
Que tenga un buen día.
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