There seems to be a similar statement under the majority of truth tables associated to flip flops “both outputs will remain low as long as set and reset are low, but the output states are unpredictable if set and reset go high simultaneously”. Does this mean there should be a delay between setting SET and RESET high? You may use MC74HC11SA as an example.
Hello wil, welcome back to the DigiKey TechForum.
The closest match to that part number I found in our system, is MC74HC112A.
The way I understand that statement, is there should be a delay in making the SET and RESET to a High input, because if they are set High at the same time, the output states will be unpredictable.
Maybe one of the engineers can add to this post with their knowledge about this.
Good luck with the projects.
Hi David,
Thanks, this validates my assumption.
Hi David,
I was thinking about it a little more but do you know why this occurs, does it have to do with set up time or hold time? anyone can chime in!
I am unable to find this information. We will have to wait if more people respond.
okay, I’ll continue to wait.
The SET and RESET inputs command opposite results at the device’s output(s). To assert both simultaneously is a logically invalid input that would likely result in destruction of the device were protections not included to avoid that result.
Cancellation of the invalid state by simultaneous de-assertion of the SET and RESET inputs amounts to a command for “No Change” per the function table. Since the prior result was invalid, an indeterminate outcome of such a command is a reasonable and expected result.
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Thank you Rick.