How to Plot Switching Supply Efficiency With a Stepped Load Current
This can be done using techniques demonstrated in the LTspice Tips on BI and BV Arbitrary Source Examples and Mathematical Integration along with simulation parameter stepping. Setting up a simulation for this that works isn’t particularly difficult, but setting one up that works well and that runs fast enough can be a bit tricky. Switching supply simulations are notorious for having convergence problems and excessive simulation times due to their nature of having rather large dv/dt and di/dt nets switching at high frequency, which is something SPICE can struggle with. The good news is that LTspice, probably due to Linear Tech’s vested interest in selling their switching supply controller ICs, does a pretty decent job of this relatively speaking to other SPICE packages I’ve used.
In the interest of giving a simple, straightforward, and useful example, I’ve started with the LTspice example circuit for the popular LT8300 flyback converter which Wurth Electronics offers several off-the-shelf flyback transformers for (including the 750312366 approximated in the simulation).
Download LTspice File - LT8300_DC1825A_Efficiency.asc (3.8 KB)
The only schematic edit I made was to change the load from a resistance to a load current. I also, of course, added the necessary BV sources ( B1 and B2 and their 1 Ohm loads) to accomplish the necessary integration of the instantaneous input and output power, effectively expressing the running average of the energy in and energy out as node voltages ( Pin and Pout ). Note that the additional parameters of the idt() functions, " 0, 1-u(time-4m) ", result in the startup period (before steady-state is reached) for the switching supply simulation being ignored. This is desirable because it’s the steady-state efficiency that is of interest, and if the startup period isn’t thrown away the simulation would have to be run for a much longer time period for the average energies in and out to appreciably settle (greatly increasing simulation time).
The other changes to the simulation shown are mostly to try and get it to run as quickly as possible. This includes the 1 Ohm load resistors on the BV sources, the .tran statement that only runs to 5 ms and only keeps data after 4.9 ms, the startup modifier along with the .ic statement to set the input and output voltages, the exclusive .save statement, and .option fastaccess statement. The .step statement creates a parameter simply called “load” that is used to control the load current ( I1 ) with a linear step of 50 mA starting at 50 mA and ending at 250 mA.
The simulation is still less than lightning fast due to the number of switch cycles required to throw away before steady state is reached, and due to the fact that effectively five different simulations are done at the different load currents, but when it does finally finish (my PC took about 30 minutes to finish), the results can be plotted as shown below.
The bottom plot simply acts as a color key for the load currents that were simulated. The output voltage is shown (with a long enough timescale to show plenty of switch cycles) to verify that steady state has been reached for each load current. The top plot of V(pout)/V(pin) are the efficiencies at the various load currents. If the simulation was run much longer the ripple in the efficiencies would become less and less, but this is sufficient to be able to clearly see the average values that are being converged on, and extending the simulation period of course extends the simulation time.
So, it can be seen that at the lightest load of 50 mA (green line), the efficiency is about 80%. The efficiency increases and peaks at almost 87% at the 200 mA (light blue line) value that was simulated, but then begins to drop of slightly again at the final 250 mA (purple line) full load. These techniques should be applicable to any switching supply you wish to simulate in LTspice, even those with multiple output windings as long as you add all the output energies, and as long as you can find ways to practically limit the necessary simulation time like in the example above.
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