LTspice Simulation

I’m working on a dc to dc converter that has 2 12V output rails and 1 5V output rail. I’ve got my circuit design and i get the expected output, however when i add a load the voltage changes. Can anyone help me figure out what i can do to keep the expected output.

How can i add a resitor load that changes but keep the same voltage output of 12V and 5V.

It appears that you’re attempting to model the gross behavior of the device as well as the output trim functionality, using an NPN transistor in linear mode to approximate the regulation behavior.

I suspect that the transistor model selected is causing issue; the generic transistors in LTspice don’t seem to behave in “ideal” fashion. I’d suggest perhaps omitting the transistor model in favor of an idealized source.