Even though LTSpice has a few “behavior logic gates” it is nice to have a collection of the basic gates with the standard number of inputs and ports for power supply (some systems use 5V, some use 3V3, some use other source references). Keep in mind there are probably several models available that may function better online, this is mostly for experimentation and understanding how combining NAND gates can result in all basic logic gates. You will first want to take a look at this post I made earlier on logic gates using MOSFETS: A MOSFET Model of a NAND Gate if you are not familiar with how a NAND gate can be modeled. There will be a download for all symbols and schematics at the end.

# Model of NAND Gate With Spice Directives

The end diagram will look like this, I will cover the specifics below:

# Custom MOSFET Models

Even though LTSpice has a large collection of components in the library, sometimes it is better to define components using specific parameters. The MOSFETs used in my forum post above use specific values to ensure proper behavior. The program has two models that allow custom parameters: pmos4 and nmos4

You will want to make sure to rename “M4” to something unique so you don’t mix them up for the “Model” name. The “model” by default is PMOS and NMOS. I renamed them to PMODA, PMODB, NMODA, and NMODB.

## MOSFET Parameters

The following parameters at minimum must be included: KP (transconductance), gamma (bulk threshold parameter), phi (surface inversion potential), lambda (channel length modulation), L (length of channel), W(width of channel), and VTO (zero-bias threshold voltage). To add custom values to these parameters you need to add a spice directive for the NMOSFETs and PMOSFETs by pressing the “S” key. The entry will be :

` .model yourModelName nmos (KP=200u GAMMA=0.9 phi=0.6 lambda=0.02 VTO=0.7)`

Change “yourModelName” to something else unique, I used NMOD1 and PMOD1 respectively. Place the spice directive somewhere on your diagram. Press the “S” key again and add this for the PMOSFET:

`.model yourModelName pmos (KP=100u GAMMA=0.9 phi=0.6 lambda=0.02 VTO=-0.7)`

Place this somewhere on your schematic.

To edit the length and width of each MOSFET channel, right-click the MOSFET in question. The P-MOSFETs share the same values:

Again, change “yourModelName” to the one you typed in the spice commands. Mine would have been PMOD1 for the P-MOSFETs and NMOD1 for the N-MOSFETs.

The N-MOSFETs have slightly different lengths and widths. The top one (NMODA in my diagram) has these values:

The one below it (NMODB):

Make sure to use the same model name as both SPICE commands otherwise the program doesn’t know what parameters to use.

# Output SPICE Directive for Simulation

One other SPICE command is added: `CL Out 0 1p`

. This is a shortcut to tell LTSpice that you want some kind of capacitance and inductance on the output. Out refers to the output, 0 is the amount of inductance present and 1p is the amount of capacitance present (backward from the letters). This is done sometimes to help the program simulate a little quicker.

# Finish the Model With Making a Symbol

Follow the steps you’d normally take in making a hierarchical circuit to develop a symbol, again here is a link to a post if you’ve never done this: Making Sub-Circuits / Hierarchical Circuits in LTSpice - Support / Tech Tips - Engineering and Component Solution Forum - TechForum │ Digi-Key (digikey.com) I did not use the “Netlist/Library” method. You can make a pretty accurate drawing using Arcs,Lines, and pins in the symbol editor. Here is what I got mine to look like:

# Modeling the NOT Gate

Now that you have a NAND gate, you can actually model the NOT gate two ways: MOSFET design or use a singular NAND gate.

Using one NAND gate in a new sub-circuit will take less effort, here is a quick diagram :

Basically, if you make both inputs tie to one input, it exhibits the same behavior as a NOT gate.

Here is a circuit diagram using MOSFETs:

The SPICE models used for the NAND are the same. The NMOD1 transistor has the same length and width settings as the lower transistor in the NAND gate. Here is the symbol I made for the NOT gate (I used the MOSFET model):

# Derivative Gates: AND, OR, NOR, XOR, XNOR

You can make all the other gates using just NAND gates or a combination of NOT and NAND gates. I will provide diagrams below just to show the layout if you are making them yourselves. You can decide how you want to design the symbols. After this section, I’ll provide a download for all the schematics and symbols I made for convenience. Put all files in a folder you linked in LTSpice otherwise they will not work.

## AND

## Files for Gates

Here is a zip folder of all the symbols and schematics I made:

GATES.zip (4.9 KB)