Modeling PLC Digital Inputs: Transitioning from the Microcontroller to the PLC World

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Many of you are transitioning to the Programmable Logic Controller from a microcontroller and digital logic background. That’s wonderful news but comes with a set of misunderstandings about the nature of the PLC and how it is connected to the physical world. In this article, we will identify the logic level thresholds with results presented in a familiar go no-go boundaries for logic-1 and logic-0. We will also measure the input resistance. Armed with this knowledge you will be able to correctly connect field devices to the PLC. You will also understand why PNP sensors are the preferred devices. At the same time, you will better understand how NPN type sensors may be used if we account for the PLC input resistance.

Figure 1: Test setup used to measure a PLC’s logic level thresholds and input resistance.

Logic Thresholds

The physical test setup is shown in Figure 1. The Crouzet Millenium Slim PLC was chosen as a representative component. Two power supplies are required. The one on the right provides 24 VDC to power the PLC. The variable supply on the left is used to provide a test voltage to the PLC’s input pin. The PLC is programmed to turn on the green indicator lamp when the digital input is above the logic-1 threshold.

By changing the variable supply voltage, we can determine when the green indicator lamp’s turn on and turn off points. The results are presented in Figure 2. All voltage below 9 VDC are recognized as a logic-0 while voltage above 11 VDC are recognized as a logic-1. The band between 9 and 11 VDC is indeterminant. The PLC displays a form of hysteresis where it takes 11 VDC to turn the device on while the voltage must drop to 9 VDC to turn it off. This is desirable as it provides a crisp transition and likely prevents indeterminant (chattering) digital input detection.

Figure 2: Diagram showing the PLC’s logic thresholds where 11 VDC and above is a logic-1 while 9 VDC and below is a logic-0.

Tech Tip: You may have encountered hysteresis in a class dedicated to op amps. Recall the comparator circuit, it uses a form of positive feedback to make an output that is “sticky.” The output of the op amp based comparator stays in one position until the input voltage crosses a threshold, it then toggles and remains “stuck” in the new position until the input swings hard in the other direction. The result is a system relatively immune to noise.

Input Resistance

The test setup for measuring input resistance is shown in Figure 3. A 10 kΩ series resistance is added between the PLC input and the variable power supply as shown in Figure 3. This resistor can be seen installed in the terminal blocks to the right of the PLC in Figure 1.

Figure 3: Schematic showing the PLC’s digital input resistance as approximately 12 kΩ. There will be a voltage drop across the test series resistance.

In a recent test, a 19.3 voltage was injected into the series resistor as show in in Figure 3. There was a corresponding 8.94 voltage drop across the 10 kΩ series resistance implying a current of 894 uA calculated as:

I_{in} = \dfrac{8.94 \ V}{10 \ k\Omega} = 0.894 \ mA

A 10.44 voltage was then measured across the PLC. The resulting input resistance is calculated as:

R_{input} = \dfrac{10.44 \ V}{0.000894 \ A} \approx 11.7 \ k\Omega

Both the input voltage threshold and the input resistance closely align with the Crouzet PLC’s datasheet.


Using the language of microcontrollers, the PLC digital input has a pull-down resistor.

  • Unconnected PLC inputs are acceptable. They will be read as a logic 0.

  • Switches and sensors must pull the input resistor up to the 24 VDC rail. In doing so, they must supply approximately 2 mA.

  • Our previously used 5 and 3.3 VDC logic is not compatible with the PLC. However, these may be used with the PLC’s analog inputs – perhaps a topic for another article.

  • PNP type sensors are preferred because they are designed to pull this input up to the 24 VDC rail. NPN devices that pull down to ground will not work unless a low value resistor is added. This external pull resistance must be sized so that the resulting voltage divider places the idle voltage well into the logic-1 area as shown in Figure 2. This PNP vs NPN distinction and solution is further explained in this previous article.

Please share your comments and suggestions in the space below.

Best Wishes,


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