Created by Scott Larson, last modified on May 09, 2012

# Introduction

Design conditions often limit the hardware peripherals available for an embedded system. Perhaps the available hardware UARTs are already allocated, or the system requires alternate functionality (creating a conflict when the UART shares a common pin). Implementing the UART in software is one common solution.

The Microchip MPLAB C18 C Compiler Libraries include software UART functions. Implementing this UART requires the user to calculate and meet the specific timing requirements for the desired baud rate. This application note provides information on the time delays required in the serial data sampling routines and the relationship between the sampling rate and the serial data.

# Background

The MPLAB C18 compiler features both hardware and software libraries for each communications peripheral found in Microchip’s PIC18 family of microcontroller products. The hardware libraries take full advantage of port registers and assigned port pins, while the software libraries allow the user to specify and configure GPIO pins as a communications port. Familiarity with the MPLAB IDE environment, the MPLAB C18 C Compiler, and RS232 is assumed.

The default library functions expect a host serial port configured for 8 data bits, 1 stop bit, no parity, and no flow control. Microchip provides all of the assembly files for the library, so the developer can modify the configuration and/or port pins.

# Application

The C18 library provides functions for initializing ports and transmitting/receiving serial data. However, the embedded developer must provide the delay routines used by the library functions, namely *DelayTXBitUART* , *DelayRXHalfBitUART* , and *DelayRXBitUART* . These routines set delays that correspond to the bit periods during communication. This provides a means to synchronize data transfer and sample received data.

Incoming data is identified by continuously polling the receive pin. A high-to-low transition indicates the start bit of the serial data frame. A half-bit delay sets the sample point at the start bit’s midpoint. After the initial half-bit delay, full-bit delays are used to sample the remaining data. This is repeated for each frame of received data. Figure 1 illustrates this technique for one frame.

**Figure 1.**RS-232 Logic Level Signal Sample and Delay

Contributing factors to sampling error include the initial response delay to the start bit, the half-bit and full-bit delay inaccuracies, and the transmitter and receiver clock tolerances. Each factor contributes a small Δ *t* from the ideal sample point of each bit. These deviations accumulate over the entire data frame and can shift the sample point before or after a data bit position, resulting in data recovery errors. Some analysis is required to assure reliable communication.

## Initial Response Delay

The initial response delay t *ird* is the maximum time between the start bit’s transition and its detection. It is determined by how often the receive pin is polled. Therefore, the number of instructions executed by the microcontroller between polling samples influences the size of the initial response delay. t *ird* contributes a one-time sample offset to each data frame. Figure 2 illustrates the timing errors. Use equation (1) to calculate the time delay provided by the polling routine.

**Figure 2.**Sample Point Change

For example, a nominal clock frequency *F* *osc* of 4MHz and 3 instruction cycles in the polling routine results in a t *ird* of 3us.

## Receive Half-Bit and Full-Bit Delays

The receive half-bit and full-bit delays determine the number of instruction cycles required for any oscillator and bit rate combination (see also the C18 library documentation, Chapter 3.6). Equations (2) and (3) define these relationships, respectively.

For example, a nominal clock frequency

*F*

*osc*of 4MHz and a baud rate of 9600bps require a half-bit delay of 44 instruction cycles and a full-bit delay of 91 instruction cycles.

Use equations (4) and (5) to calculate the time delay provided by the half-bit and full-bit instruction cycle delays, respectively. For the example above, the half-bit time delay is 53us, and the full-bit time delay is 105us.

For received data at 9600bps, the total time period (1 start bit, 8 data bits) is 937.5us, with the last data bit’s center point at 885.4us. Sampling the incoming data requires 1 *Thalfbit* and 8 *Tbit* delays, totaling 893us. The sample point of the last data bit is offset by approximately 7.6us from the center of the bit period.

## Clock Tolerance Error

The clock variation between the transmitter and receiver also contribute to the sampling error. Clock error *Tcte* is the time between the sample point and the nth data bit of the transmitted data frame. The sample window bounded by *Tcte* *upper* and *Tcte* *lower* varies, since microcontroller internal oscillators can vary by ±2% at ambient and ±10% over the operational temperature range. *f* *max* and *f* *min* are the worst case clock frequencies in the application’s environment. Equations (6) and (7) determine if the final sample occurs before the end of the nth bit of the data frame.

*nbits* is the number of bits in the packet (including start and data bits). Equations (8) and (9) ensure that the sample takes place after the nth bit begins.

Assume a host transmit bit rate of 9600bps, 9 bits to recover (1 start bit, 8 data bits), and a 4MHz clock with an accuracy of ±2%. The receiving microcontroller’s clock of 4MHz also has an accuracy of ±2%. Using equation (6) and (8) results in *Tcte* *upper* = -15.6us and *Tcte* *lower* = 17.7us, meeting the timing boundary conditions in equation (7) and (9).

With the transmit clock accuracy decreased to ±4 %, *Tcte* *upper* = 2.0us and *Tcte* *lower* = 0us, failing the boundary requirements, resulting in communication errors at the worst case clock frequencies.

## Total Receive Error

Total receiver error *Ttre* is the sum of the initial response delay, the half-bit and full-bit delays, and the clock tolerance error. In effect, the sample window, bounded by the clock variation, is shifted in time due to the accumulation of timing errors. This shift can cause the sample window to fall outside the data bit boundaries, resulting in communication errors. Equations (10) and (11) determine if the final sample occurs before the end of the nth bit of the data frame. Equations (12) and (13) ensure that the sample takes place after the nth bit begins.

Expanding on the prior example, assume a host transmit bit rate of 9600bps, 9 bits to recover (1 start bit, 8 data bits), and a 4MHz clock with an accuracy of ±2%. The receiving microcontroller’s 4MHz clock has an accuracy of ±2%. Applying the results from equations (1), (4), (5), (6) and (8), in equations (10) and (12) results in

*Ttre*

*upper*= -15.6us and

*Ttre*

*lower*= 17.7us, meeting the timing boundary conditions in equation (11) and (13).

Accumulated timing effects can move the sample point to the edge of the bit period. Noise on the line or capacitive effects altering the signal edge rate can further reduce the sample margin until data is not reliably recovered.

## Transmission Full-Bit Delay Error

Data transmission from the target also introduces timing errors from the full-bit delay inaccuracy and clock tolerance. The transmit full-bit delay, equation (14), determines the number of instruction cycles required for any oscillator and bit rate combination. Equation (15) calculates the time delay provided by the full-bit instruction cycle delay.

For a microcontroller clock frequency *F* *osc* of 4MHz and a baud rate of 9600bps, a full-bit delay of 93 instruction cycles is required. The full-bit time delay is 105us.

Transmission timing errors accumulate as the start bit, 8 data bits, and stop bit are transmitted and may impact the ability of the host receiver to recover the data.

# Conclusion

A conservative timing margin must be maintained to ensure reliable data transfer. If high bit rates are required, a tight clock tolerance enhances the timing margin. Increasing the clock frequency reduces the software half-bit and full-bit delay inaccuracies. Reducing the serial data rate provides longer bit periods, increasing the timing margin.

Using software UART is not without pitfalls. But, once the contributing error factors are understood and ameliorated, a reliable serial communication port can be implemented using any pair of GPIO pins.

# Additional Information

MPLAB® C18 C Compiler Libraries, Chapter 3.6; Microchip Technology, Inc.