Receiving single-lane MIPI CSI data

Hi all, I’m very new to working with MIPI CSI2. I’ve searched around for the answer to this, but haven’t been able to get far without access to MIPI specifications — apologies if these turn out to be very basic questions.

I’m designing for an Omnivision image sensor. I can’t share the datasheet or specific details, unfortunately, since it’s confidential with Omnivision.

The chip uses a single-lane MIPI data output. The D-PHY connector on the Raspberry Pi is for 2-lane MIPI data transfer.

Can I simply connect the sensor data output to one lane of the Raspberry Pi, leaving the other Pi lane disconnected? And would doing so require any special drivers? Or alternatively, would I need to use some kind of MIPI receiver/decoder to convert to a different protocol that the microcontroller can receive?

Further, are MIPI voltage levels standardized? The chip I’m using has a 1.5 V MIPI voltage supply.

I’m hoping to use an FSA641 MIPI bridge (unless anyone has a better suggestion for receiving data from multiple cameras). A diagram from the bridge datasheet would seem to indicate that the single-lane and dual-lane are compatible in this direction, but this may be misleading.


Thank you in advance for the help!

Hello anuj,

I’ll preface this by saying I’m also fairly new to MIPI and don’t have access to the spec, but I think I can provide some insight.

It should be fine to leave one of the lanes disconnected/idle, but I suspect you will need to adjust the software to accommodate. The number of lanes is just how many bytes are received at a time, so the Pi needs to know to expect one byte instead of two per transaction. I would guess doing this at the driver level, if you’re able, would be the most efficient. Alternatively, you might be able to filter out the final result at the application level because you know that every other byte (the one from the disconnected lane) is dummy data.

I believe the standard signaling level for MIPI is 1.2V but it seems the actual supply voltage can vary. The board I’m currently working with uses a 1.2V supply. Borrowing an example from Xilinx:

Hope this helps.

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Thanks @Taylor_1236, that’s extremely helpful! Bandwidth isn’t an issue, so ignoring every other byte seems like it would be the most straightforward solution. And great to hear that we shouldn’t need to worry about voltage translations either.

The ICs on that link are very interesting too. Ultimately, we hope to interface with nearly 100 sensors that have single lane outputs, and we need to avoid needing to use more than a few controllers. Do you have suggestions on the best way to receive data from all of those sensors, perhaps using layered switches/multiplexers/bridges? Or would something like that receiver IC be able to convert to a more useful protocol for interfacing many sensors with one controller?

100 image sensors on a few controllers? I’m not sure about a “best” solution. The first thing that comes to mind is an FPGA with a large number of differential I/O. With that, you could make a large mux network within a single IC and create a pass-through switch effect like the FSA641 but at a larger scale. I don’t know if this would be a cost-effective solution, but it might be something to look into.

An FPGA could give you the flexibility to convert protocols as well if that’s something you need to do, but I can’t think of one off the top of my head that would be more useful. In that case, you would need one with a D-PHY to properly receive the MIPI data before conversion.

Hmm I see, an FPGA is likely a longer-term solution that we’ll look into. In the shorter term, do you know if an integrated mux like the FSA641 can utilize pass-through in the same way and be layered i.e. connect both outputs of one mux to two other muxes? And/or are you aware of any larger muxes, like 4:1?

Unfortunately, I haven’t been able to find any MIPI muxes bigger than 2:1. However, the layering is certainly a valid approach and could work. You just end up with a lot of muxes. The only thing I would be concerned about is each layer is going to add a certain amount of impedance to your signals that could become significant as the number of layers increases. Though at lower bandwidths this shouldn’t be much of an issue.

I see, and this impedance would matter for the RC time constant? Hence why it may cap max transmit speed?

Yes, each switch adds parasitic resistance and capacitance to the signal line. So the more switches your signal has to pass through before it reaches it’s destination, the lower the final signal power and max bandwidth will be. But as long as the receive is sensitive enough to make up for the losses, the circuit can still function.