Lattice cross link application note for LVDS to CSI2 interface

Support
1

Dear All,

We want to use for one of the sensor, LVDS to CSI2 Lattice crosslink IC+FPGA.
Would like to understand the interface details. Attached the plan of how we want to use.

image
image1991×542 107 KB

Kindly share the interface protocol details or application note if any for this usecase.

Thanks and Best regards

Mani from NXP

2

Hi,
Welcome to the Digikey tech forum . You may find some useful information linked here

3

you may be searching for this link:

https://www.latticesemi.com/view_document?document_id=51679

FPGA-IPUG-02006-1-4-SubLVDS-MIPI-CSI2-Image-Sensor-Interface-Bridge User Guide FPGA-IPUG-02006-1.4 from Lattice Semiconductor Corp. April 2019.pdf (2.0 MB)

4

Hello Steve, Hello Rolf,

Thanks a lot for the prompt replies. Sorry to come back late as I was out of office. The links shown are subLVDS to CSI2.
Could you please indicate document capturing plain LVDS to CSI2.
Basically I wanted to know, DDR data transfer protocol interface. Our sensor interface is shown above with bit_clk (lvds clk), frame_clk indicating valid 10 bit data clock and lvds_data_valid signal to indicate the complete line data (total data for every line=3203220bits converted to 10bit raw sample). Outside valid data, plan is to send the sync/idle data.

It would be helpful, if you could share the detailed protocol interface for the LVDS RX interface. Thanks a lot for your support.

If possible for a call to discuss by some means, that would really help.

5

The only other info I am finding is MIPI DSI/CSI-2 to OpenLDI LVDS in the link below if you need further information you can use the contact us at the bottom of the page under support .

Thanks Craig

6

Thanks Craig. Lattice crosslink doc says sublvds/lvds to CSI2. So I assume it has support for LVDS input and CSI2 output. I will try your suggestion of contact us

7

Let me add a few final comments:

Input side

  • LVDS can be supported as an interface standard
    Only the protocol is not quite clear at the moment, you are talking about RAW10 and CRC.
  • Ideally, you can go directly to the pixel to Byte block, otherwise you have to make a small modification to the input data.

On the output side

8

Hello Rolf and others,

Is it possible to get the code for simulation package with the scripts included?
Or that is possible only after the purchase? Especially I am trying to understand the LVDS protocol supported.

Another question what is the LVDS IO signalling level? 1.8V supported or 3V3?

Still not able to find the way to contact the support directly. If there is a possibility to have teams call (manikandan.pachapakesa@nxp.com), that would be great. Sorry to annoy with lot of questions.

Thanks and Best regards

Mani

9

Sorry Mani,

your provided email did not work:

manikandan.pachapakesa@nxp.com was undeliverable.

Please can you verify and come back to us again.

In general, all their IP Cores can be simulated prior to the purchase of IP licenses.

LVDS signaling levels are defined in the datasheet.

Can you also tell us in which time zone you are working in ?

Thanks and Best regards

Rolf

10

Hello Rolf,

It is my bad. manikandan.panchapakesa@nxp.com (I missed n earlier)
I work in Indian time Zone (Bangalore). I am ok with any late hours call.

Thanks and Best regards

Mani