RVfpga: Understanding RISC-V Architecture and Implementation on an FPGA

Semiconductor Integrated Circuits (ICs)
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Webinar Recording:

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Summary

Join DigiKey for a close look at the inner workings of the RISC-V processor core and ways to implement a soft RISC-V processor core in a target (Xilinx) FPGA device. The RVfpga webinar covers the foundational knowledge that the next generation of Programmers and Engineers need to harness the potential of RISC-V. Digi-Key is proud to sponsor this webinar in collaboration with Imagination Technologies featuring Prof. Sarah Harris (UNLV). The webinar attendee will learn how to:

  • Target a commercial RISC-V core and system-on-chip (SoC) to an FPGA
  • Program the RISC-V SoC
  • Add more functionality to the RISC-V SoC
  • Analyze and modify the RISC-V core and memory hierarchy

After completing the RVfpga webinar, attendees will walk away with solid understanding of a commercial RISC-V processor, SoC, and ecosystem.

If you can’t attend the live webinar, be sure to still register as we’ll send you the recording afterward! This webinar will be in English only.

Speaker

Sarah L. Harris
Associate Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas

Sarah L. Harris is an Associate Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas. She earned her M.S. and Ph.D. at Stanford University. Before joining UNLV in 2014, she was a faculty member at Harvey Mudd College from 2004-2014. She has also worked at Hewlett Packard, Nvidia, and the Technical University of Darmstadt and has collaborated with other companies including Southwest Research Institute, Intel, and Imagination Technologies. She is the co-author of three popular textbooks: Digital Design and Computer Architecture, 2nd Edition (2007), ARM Edition (2015), and RISC-V Edition (2021). Dr. Harris is also currently leading or co-leading two NSF-funded grants on Smart Cities and on integrating family support in STEM education. Her research interests include computer architecture and applications of embedded systems and machine learning to biomedical engineering and robotics.

Software, Processor/FPGA Boards, and Resources

Vivado Download

Vivado_20192
Vivado_201921610×750 50.6 KB

Vivado_Version
Vivado_Version1242×1030 129 KB

Vivado Download - Windows

Windows
Windows1204×236 26.7 KB

Vivado Download - Linux

Linux
Linux1100×186 24.1 KB

Vivado Setup

  • Vivado HL WebPACK

vivado_defaults

  • Nexys A7 Board drivers (optional)

Vivado Install Digilent Board Files

vivado
vivado819×238 13.6 KB

Vivado → Tools → Settings:

Vivado_Settings
Vivado_Settings1215×747 24.4 KB

Hardware

Nexys A7-100T Artix-7 series FPGA Evaluation Board

Guides

Guide: https://university.imgtec.com/rvfpga/

Forum: Imagination University Programme Forum – Imagination University Programme

Q&A from Webinar

How does platformIO build the bitstream on NEXYS A-7 directly, without synthesizing and implementing the design?

  • We provide the bitstream for the baseline SoC, which you can use. We also provide the SoC sources so that you can build it in Vivado, as we explain in detail in Lab 5.

Yes, but how does the new instruction memory contents are updated on the baseline SOC using PlatformIO?

  • We install a platform provided by Chips Alliance on top of PlatformIO which includes the toolchain, openocd.

How do we access these lab files? Will they be posted on Github?

Do you provide source code for RVfpga? or just a bitstream?

  • Both

Do you know if support for Basys3 board will be available by 1 month from now?

  • We don’t know exactly, but it should be available in the next months. Please contact us directly and we’ll share more details.

Completely misleading webinar title, this has ABSOLUTELY NOTHING to do with the RISC-V architecture, it is simply showing how to use a dev board! COMPLETE WASTE OF TIME!

  • I’m sorry, about half way. Sarah is going to go over adding addition cpu instructions to the core and working with ventaltor.

For the Q&A section: Will these slides be available after the presentation?

  • Hi, yes, we will provide the slides with the recording after the webinar today.

Assuming I have a similar board to Nexys7 (Arty7) and solid background in Vivado, how easy is it to edit the development environment to support the board available to me?

  • Hi, what FPGA in on your board? the design takes about 55% of the A100-T… (the A35-T would be too small). The problem is that the SoC may not fit in the FPGA. We will soon provide a smaller RVfpga version, based on EL2, that will fit in Basys 3 or Arty A7.

A100-t

  • I also have that board, I’d also like to see the RVFpga also done on it… I’m not 100% sure what’s missing, just need to spend more time on it.

Is the course offed at distance?

DDOn’t see the updated slide

  • If your screen has froze, please refresh your browser.

What about the compiler? It is available in the material?

  • It’s actually gcc, provided thru platform io

imgtec link not working?

Are the bit instructions part of this yet?

  • They are not included in EH1 but we include exercises in Lab 18 where we ask the user to include them.

Can I use C%2B%2B with VS Code?

  • c++ is supported thru the gcc-RISC-V toolchain used.

I use it with my current STM32 chips?

  • Sadly no… To run this version of the RVFpga, you’ll need an FGPA.

I thought the RISC-V HW code was VHDL, not Verilog? Are you just using that as the tool?

  • SweRV EH1 and SweRVolf, in which RVfpga is based, are written in Verilog.

Is there a time cost to Gshare BP or is this parallel to execution?

  • The BP is part of the Fetch Stage.

I assume that there is a configuration file for the visual studio IDE, correct? I always spend a lot of time fighting those kind of set up issues.

  • In this case we utilize Platformio to do the heavy lifting of the project setup for this Design.

What problems arise on 2020 versions? Won’t compile? Or other configuration variables mismatched? etc

  • It’s been tested in 2020 (dot something) by somebody and it also works, with a minor change that is detailed in the Imagination Forum.

Is closed captioning available?

  • We do not have closed captioning today.

Is everyone having connection issues?

  • Hi, it’s playing ok on our other systems. Can you try to refresh your browser window to see if that helps.

Is it possible to use a different FPGA aprat from Nexys A7?

  • There are but, we will have Sarah expand on this in the Q/A section!

Will digilent Basys3 board work? a board similar to Nexys

  • Right now this cores over 50% of the A100T, the 35T would be a challenge…

What is your C compiler? gcc? or LLVM backend?

  • right now platfomio used gcc

Are these labs downloadable? I see the tools for the labs are available but I don’t see the labs RVfpga: Understanding RISC-V Architecture and Implementation on an FPGA

What is the native bus for RISC-V?

  • SweRV EH1 includes both AXI4 and AHB buses. We use AXI4 in RVfpga and Wishbone for the peripherals.

Pls suggest what I can do at bachelors level in my final year project using RISC V

  • Anything where a processor can handle background tasks. Such as touch screens, interfacing with other devices, system monitoring. The FPGA is best saved for parallel computation tasks.

Can you give a brie roadmap on how to follow the touch screen processor project?

  • There are many such projects already online for many processor types, likely including RISC-V. They should be easy to find via search engines.

This is board specific? As in can’t we transform this implementation onto another board like Nexys 200T?

  • It entirely depends on the resources available on the target device. Compare the FPGA with that on the Nexys A7. If the device on the 200T is bigger then it should port.

For the recommended board being used, about what percentages of resources does it take to do a FULL implementation of the processor /

  • The current implementation takes up 50% of the Nexys A7 Artix-7 FPGA. I’d gather any added features will take up more resources.

I’m sorry, what did you say about using Wishbone bus, as oppsed to using the AXI bus ?

  • Our core uses AXI4 bus and the peripherals use the Wishbone bus.

Few questions, I’m confused. This just looks like really basic embedded RISC C/ASM programming. Where does FPGA come into play and when is VHDL used?

  • Labs 1-4 are about C/asm programming. Labs 6-10 are about using and adding peripherals, for which you need access to the Verilog code. Labs 11-20 analyse and modify the processor, which also needs access to the Verilog code.

When discussing the virtual debugging and VMWare was mentioned as being use, is VMWare a requirement, or can VirtualBox be used to host VM?

Do you have to be affiliated with an academic institution to download and run RVFPGA or can an individual sign up on their own?

  • Nope, just say end user. All submissions are reviewed by 2 users at Imagination. They are mainly education driven, hence all the questions. but they fully understand.

is the instruction set of the risc-v composed of 32-bit and 16-bit instruction such as for Cortex-M processor? or only 32-bit instructions?

  • It includes both 32-bit and 16-bit instructions.

Is it possible to create new instructions or modify the existing one? Is everything open source?

  • Yes, everything is open source. Lab 18 shows how to include some new instructions.

Can you spell the name of the mounting board that you just mentioned?

What is the advantage of using virtual RISCV on an FPGA rather than a silicon RISCV?

  • You can view and analyse the SoC. You can even change the SoC (use other configurations, extend the microarchitecture, add peripherals…).

what was the motivation behind using the SweRV Core instead of a simpler core with a 3 or 5 pipeline stages ?

  • SweRV EH1 is a very powerful core which includes interesting microarchitectural features. We plan to add a smaller version of RVfpga based on EL2, a core with 4 pipeline stages.

How should I access the material? Is it teaching material download via Training and Teaching Resources - Imagination University Programme

  • Correct, it’s available there, but it’s behind a sign-up wall. There are 2 Imgtec developers that manually approve access…

The imgtec university teaching material requires an application registration with details on the project and number of people …etc, why this is needed?

  • Imgtec, normally has university professors looking to build course with this material. Just answer honestly, the 2 Imgtec users who are going to approve requests fully understand it’s odd for normal developers.

Hello, it’s only with Verilog langage?

  • Yes.

are all 20 labs ready now, or just the first part?

  • The full project, has all 20 labs…

What kind of clock speed can the RVFpga core operate at in the Artix7 FPGA?

  • We use a 50MHz clock.

how does imagination technologies see making money from developing this core? selling training? struggling to figure out how it happened and is sustainable

  • So, the RVFpga, is actually the ip used in “newer” SGX cores… They see supporting RISC-V opens more doors for their IP to be used…

Any participation certificate

  • Thanks for inquiring. We do not offer certificates for this Webinar.

Is the RVFPGA course available working engineers not just students? If so, where?

No luck gaining access. References to “university” throughput the page.

  • Just fill it in as a end user… The page was heavily written for universities, but behind the scenes two developers from imgtec is approving the docs…

Do you provide licenses to use the rvfpga material in a university class?