Smart demux?

Is there a component that works like a demux but holds the last know value on all outputs?

Basically, I am trying to find a way to send a signal from a FPGA (with limited I/O) to a break out connector with more IO than the FPGA can offer. For example, I would like the connector output to constantly drive signals A and B, but I control them from one pin on the FPGA.

Thank you for the help!

Several approaches to the problem exist; products in the I/O expander family being perhaps the most obvious, with plain 'ol shift registers being another option.

Regardless of component choice, I/O expansion imposes throughput limitations; consider carefully the nature of the signals you want to send through the process when making selections.

How would a shift register solve the problem? I would like to not use a protocol to communicate with it, so the I/O expander isn’t an option.

Serial in, parallel out shift registers would permit a (theoretically) infinite number of expanded output to be controlled from a handful of I/O lines, typically for clock, data, and latch enable.

Your intentions/expectations are unclear on this point, insofar as the process of condensing and re-expanding parallel data streams for transport through a narrow medium requires use of some algorithm or protocol to define the transaction.