Using the Configurable Logic Block (CLB) for Rising and Falling Edge Detection

[MCHP_MCU]

The Configurable Logic Block (CLB) in Microchip’s PIC16F13145 family of MCUs offers an efficient way to implement digital logic functions directly in hardware. One practical use-case of the CLB is edge detection a common requirement in event-driven applications where detecting transitions such as button presses, clock pulses, or data signals is critical.

By implementing edge detection directly in the CLB, you can create dedicated rising and falling edge detectors that generate a short pulse whenever a signal transition occurs. Because this logic runs entirely in hardware, it ensures fast, reliable detection without relying on CPU intervention or software polling. This approach minimizes latency, improves timing precision, and frees up processor resources for other tasks.

What is Edge Detection?

Edge detection identifies transitions in a digital signal:

• Rising Edge Detection occurs when a signal transitions from LOW (0) to HIGH (1).
• Falling Edge Detection occurs when a signal transitions from HIGH (1) to LOW (0).

Detecting these transitions is essential in applications like event triggering, and pulse counting

Implementing a Rising Edge Detector with CLB

A rising edge detector generates a short pulse when an input signal transitions from LOW to HIGH. This can be implemented in the CLB using:

• A D Flip-Flop to latch the previous state of the signal.
• A Logic Gate (AND) to compare the current and previous states and generate a pulse.

CLB Configuration for Rising Edge Detection:

1. Route the input signal to a D Flip-Flop to capture its previous state.
2. Use a NOT gate on the D Flip-Flop’s Q output to produce the inverted previous state.
3. Use a combinational logic gate (AND) to compare the current and previous state
4. Outputs a pulse when the input signal transitions from LOW to HIGH.

Rising Edge Detector Step-By-Step Guide

Implementing a Falling Edge Detector with CLB

Similarly, a falling edge detector produces a short pulse when an input transitions from HIGH to LOW. This requires:

• A D Flip-Flop to latch the previous state.
• A Logic Gate (AND) to to compare the current and previous states and generate a pulse.
  
  

CLB Configuration for Falling Edge Detection:

1. Routen the input signal into a D Flip-Flop to capture its previous state
2. Invert the current input signal using a NOT gate.
3. Use a combinational logic gate (AND) to compare the current and previous state
4. Outputs a pulse when the input signal transitions from HIGH to LOW.

Falling Edge Detector Step-by-Step Guide

Learn More:

For further details on using the Configurable Logic Block (CLB) and other embedded control techniques, check out:

Try an interactive demo that lets you experiment with CLB configuration in real time

Browse the CLB Tips and Tricks guide for practical examples and real-world use cases

Learn the basics of building digital logic using the CLB in an interactive course [Logic Circuit Design 101]

[heke]

It might be worth mentioning that the input should be synchronized to the clock domain. Otherwise all kinds of funny things may happen. Assumingly in PIC there is a register between an IO pin and CLB (apologies for ignorance, I haven’t used PIC MCUs). When implementing an edge detector on FPGA/ASIC, the input should not be taken directly from an IO.
Also, pulses shorter than a clock cycle may or may not get detected.

[APDahlen]

Thank a good point @heke - let’s call this a hard-learned lesson in metastability!

It looks like HFINTOSC is an input to the logic.

From the datasheet:

The CLC module operates independently from the system clock and will continue to run during
Sleep, provided that the input sources selected remain Active.

The HFINTOSC remains Active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected.

In other words, if the HFINTOSC is simultaneously selected as both the system clock and as a CLC input source, when the CLC is enabled, the CPU will go Idle during Sleep, but the CLC will continue to operate, and the HFINTOSC will remain Active. This will have a direct effect on the Sleep mode current.

Sincerely,

Aaron

[MCHP_MCU]

Thanks Heke.
The CLB has built-in edge detectors that also serve as synchronizers, aligning input signals to the CLB clock domain. Bypassing them can result in unstable behavior for asynchronous or fast signals.