What does SPE really mean – Single Pair Ethernet explained by Microchip

Semiconductor Integrated Circuits (ICs)
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What does SPE really mean – Single Pair Ethernet explained by Microchip

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  • It’s just an Ethernet transceiver (PHY), Physical Layers 2-7 remain the same

  • Single Pair Ethernet, SPE also referred to as ‘T1’ = 1 Balanced Pair of Wires

  • Multiple bandwidths: 10BASE-T1S, 10BASE-T1L, 100BASE-T1, 1000BASE-T1, 2.5/5/10GBASE-T1

Motivation – Ethernet is a Success Story

Security

  • List item

  • Offering reliable standards (MACsec, IPsec)

Safety

  • Preventing nodes from flooding network

  • Deterministic behavior

Synchronization

  • Single time base for all nodes

Software defined system

  • Sensors, actuators just offering a service

  • Independent applications operating on services

Wiring

  • Shorter cables through zone architecture

  • Enabling machine-made wire-harness

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No Gateways

  • Using switches instead of gateways

Multidrop

  • Fewer PHYs
  • Less cables
  • Fewer switch ports
  • Simple UTP cabling

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Scalable from Low to High Bandwidths

  • Common network software stacks

  • Physical layer (PHY) independent

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Why Single Pair Ethernet?

Single Pair Ethernet reduces system cost, weight and wiring complexity

IEEE 802.3cg – 10BASE-T1S and 10BASE-T1L

  • 10 Mbit/s connection over a single two-conductor cable

  • 10BASE-T1S: Short Reach (25m), multi-drop bus line or point-to-point connection

  • 10BASE-T1L: Long Reach (1 km), point-to-point connection

IEEE 802.3bw – 100BASE-T1

  • 100 Mbit/s over single pair cable

IEEE 802.3bp – 1000BASE-T1

  • 1000 Mbit/s over single pair cable

IEEE 802.3ch – 2.5/5/10GBASE-T1

  • 2.5Gbit/s, 5Gbit/s, 10Gbit/s over single pair cable

Networking Megatrends

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More powerful, flexible network to meet application challenges

Ethernet Trends

Zone Architecture Simplifies Wiring and Connectivity

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Ethernet is the enabler for scalable communication infrastructures

Single-Data Transmission Technology to Allow Access All Devices

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Ethernet is the enabler for connected cloud-to-edge infrastructures

PLCA

Optimized Data Throughput on a Bus Line

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Goals

  • Full bandwidth utilization

  • Reduce latency

  • Quality of Service (QoS)

Principle

  • Avoid physical collisions on the medium by organizing the media access

  • Called Physical Layer Collision Avoidance (PLCA)

How it is done

  • Only the PHY that owns a transmit opportunity is allowed to send data

  • Transmit opportunities are given in a round robin manner

  • A new cycle of transmit opportunities is started when the PLCA coordinator node sends a BEACON

  • Works on top of Carrier Sense Multiple Access/Collision Detection (CSMA/CD)

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Application Examples

Automotive Zone Architecture

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• Door
• Bumper
• Seat Zone
• Roof
• Engine Compartment
• Battery
• etc.
10BASE-T1S Enabling Zone Architecture
• Example Door Zone
• Window Lifter
• Mirror Control
• Speakers
• Lock
• Ultrasonic
• Ambient Light
• Indicator Light

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Sensors and Actuators at the Edge

Sensor

  • Ultrasonic

  • Radar

  • Microphones

  • Powertrain

Actuator

  • Light

  • Speaker

  • Electric Motor

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• Factory automation
• Sensors
• Actuators
• Assembly Lines
• Packaging

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Industrial

In cabinet racks

  • Intra-system management interface in racks

  • Fan, temperature sensor, voltage monitor, DC/DC converters, optical modules …

Control units

  • Switches (on/off), buttons, converters, relays, input/output cards …

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Building Automation

  • Lighting applications

  • Elevator

  • HVAC

  • Sensors

  • Shades

  • Solar System

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Medical

Patient Room, Operating Room and Lab Equipment

  • Smart beds

  • Vital sign sensors: temperature, pressure, liquid and gas flows …

  • Monitoring equipment

  • Backplanes in monitoring equipment for plug-in attachments

Equipment racks

  • Infusion pumps

Diagnostic Equipment

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Server

Network equipment

  • Intra-system management interface in servers and switches

  • Fan, temperature sensor, voltage monitor, DC-DC converters, optical modules …

Computer Server Backplane

  • Control plane for configuration/monitoring

  • Slots

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10BASE-T1S Ethernet PHY LAN8670B1-E/LMX / LAN8671B1-E/U3B / LAN8672B1-E/LNX

Designed according to IEEE Std 802.3cg™-2019

10 Mbps over single balanced pair

Half-duplex point-to-point segments up to at least 15 m

Half-duplex multidrop segments up to at least 25 m with up to at least 8 nodes

High bandwidth utilization and latency optimization

Physical Layer Collision Avoidance (PLCA)

  • Multiple PCLA IDs per node

  • Burst mode

  • CSMA/CD

Standard interfaces

  • MII

  • RMII

  • SMI (MDIO, MDC) for rapid register access

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Smallest footprint

VQFN packaging with wettable flanks

LAN8670 32-pin (5x5 mm)

LAN8671 24-pin (4x4 mm)

LAN8672 36-pin (6x6 mm)

Extended temperature range

-40°C to +125°C

Available with Automotive, AEC-Q100 qualification

Functional Safety Support

LAN8650/LAN8651 – LAN8650B0-E/LMX / LAN8651B0T-E/LMX

10BASE-T1S MAC-PHY Ethernet Controller with SPI

Designed according to IEEE Std 802.3cg-2019™

10 Mbps over single balanced pair of conductors

Half-duplex point-to-point segments up to at least 15 m

Half-duplex multidrop segments up to at least 25 m with up to at least 8 nodes

High bandwidth utilization

Physical Layer Collision Avoidance (PLCA)

Burst mode

CSMA/CD

Standard interface

Serial Peripheral Interface (SPI)

Designed to the OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification, V1.1

Supports clock rates up to 25 MHz

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10BASE-T1S Evaluation Boards and MPLABTM Harmony

10BASE-T1S PHY RMII Evaluation Board EVB-LAN8670-RMII

Fits to many Microchip MCU boards

Small form factor

Available from MicrochipDirect and DigiKey EV06P90A

10BASE-T1S PHY USB Evaluation Board EVB-LAN8670-USB

Makes every USB host a potential 10BASE-T1S node

Drivers for Linux

Available from MicrochipDirect and DigiKey EV08L38A

10BASE-T1S MAC-PHY SPI Evaluation Board

Enables Ethernet communication for various Microchip evaluation kits that support
click boardsTM and the SPI interface

Available from MikroE (www.mikroe.com)

MPLAB Harmony v3 Development Framework

Integration into development framework for Microchip microcontrollers and microprocessors

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Microchip 10BASE-T1S Resources

Dedicated 10BASE-T1S web page at
https://www.microchip.com/en-us/solutions/ethernet-technology/single-pair-ethernet/10base-t1s

Includes links to product pages, datasheets, videos and Microchip University Class

Introduction to 10BASE-T1S Microchip University class at
https://mu.microchip.com/10base-t1s-single-pair-ethernet-system-integration

Industry information from the Single Pair Ethernet System Alliance can be found at
Single Pair Ethernet System Alliance – Technology for the Future

Summary

10BASE-T1S technology makes it possible for low-speed devices to connect to a standard Ethernet network, eliminating the need for dedicated communication systems

All-Ethernet networks currently being implemented result in easy access to data throughout IT and OT networks, allowing software-defined partitioning, using well known security mechanisms and simplifying data analytics

Interfacing to even the simplest MCUs reduces the overall size and cost of a design

Microchip‘s comprehensive 10BASE-T1S solutions support customer and application needs with small form-factor devices, with Time Sensitive Networking (TSN) support and extended operating temperatures

Functional Safety (FuSa) Ready means systems designed with these products can meet required functional safety specifications