We use cookies to provide our visitors with an optimal site experience. View our privacy notice and cookie notice to learn more about how we use cookies and how to manage your settings. By proceeding on our website you consent to the use of cookies.
Here, I have selected the component of LTC2344-16 and my question is:
Go to Page 14, after open the datasheet of LTC2344-16.
If I use the Quad SPI (QSPI) mode, then, Which clock pin should I connect to the MCU, either SCKI (Pin19), SCKO (Pin 22). Or else, Do I need to connect both pins to MCU such as SCKI (Pin 19) and SCKO (Pin 22), to held the communication on QSPI mode?.
Same above question is repeated for Dual SPI as well…
And also, Could you please explain me why do I need to use specific pin?, Why not other pin?, Why not use both pins?.
The SCKO pin is not used for SPI when communicating with an MCU, as an MCU can generally not handle Dual and Quad data lanes. SCKO is intended to be used when connecting to FPGAs, where it is used to synchronize the incoming SDOx lanes to the FPGA.
So, you simply connect the SCKI pin (19) to the SPI clock pin of your MCU and leave the the SCKO pin (22) floating.
The “Application Information” section on page 32 explains the following:
When interfacing the LTC2344-16 with a standard SPI bus, capture output data at the receiver on rising edges of SCKI. SCKO is not used in this case. Multiple SDO lanes are also usually not useful in this case. In other applications, such as interfacing the LTC2344-16 with an FPGA or CPLD, rising and falling edges of SCKO may be used to capture serial output data on SDO0 to SDO3 in double data rate (DDR) fashion. Capturing data using SCKO adds robustness to delay variations over temperature and supply.
Just to be clear, the LTC2344-16 does not implement either the Quad SPI or Dual SPI protocols. Rather, it offers a “Serial CMOS I/O” mode which is compatible with Standard SPI (a.k.a. Single SPI).
Quad SPI buses transfer the data in a parallel fashion as shown in the example below below. Note how each byte is send in two clock cycles.
The four data lines employed by the CMOS I/O interface on the LTC2344-16, however, correspond to the four analog input channels. The conversion results for each channel are sent out in a sequential manner, as shown in Figure 17 from the datasheet (and shown below).
As described by the datasheet on page 32, the conversion results are delivered on each data line in a circular approach. For instance, on SDO0, the conversion results will appear first from channel 0, then from channel 1, channel 2, and finally from channel three. See Figure 18 in the datasheet for a clear picture of this.
Thus, even if you are using an MCU with a QSPI peripheral, you can’t use QSPI to interface with this ADC. You would have to use a Standard SPI peripheral and connect SCKI, CS, SDI, and any one of the SDOx lines. As @David_1528 mentioned, SCKO is not used for SPI communication.
Unfortunately, I cannot. The Quad SPI protocol is intended as an external memory interface. Consequently, I don’t believe you will have much luck finding an ADC that implements it.
Here, I would like to use the parallel communication on SPI, like I want through the data out from the ADC to MCU on 4 lines (such as SDO0, SDO1, SDO2, SDO3), and again send the data back to ADC from MCU on 1 line (such as SDI). For this communication, my MCU not having parallel communication support on MCU side, but I have ADC that will support this parallel communication.
Therefore, I would like to use the Parallel-In and Serial-Out Shift Registers for this communication between the ADC and MCU. Does it works?, If not, please could you suggest me the good solution for this?.
I’ll start by saying that if it is absolutely imperative for your application that the four data lines be read simultaneously, then an MCU may not be the right device for the task. As stated in the datasheet:
Multi-lane data capture is usually best suited for use with FPGA or CPLD capture hardware
That’s not to say it’s entirely infeasible to accomplish what you’re asking with an MCU, but it will undoubtedly require some skill/creativity on your part. Quad SPI will definitely not work in the situation you described above using the LTC2344-16. Even if you were willing to write the code to disentangle the received data, a fifth data line is required for the SDI signal (whereas QSPI only uses four data lines).
In the end, the solution will depend on the MCU you have chosen for your application and how many of it’s resources are allocated to other tasks. If you are using a higher-end MCU with four Single SPI instances available (which might include the Quad SPI being utilized in Single SPI mode), I can envision a solution where one SPI is configured as a full-duplex master and the others are configured as receive-only slaves. Another solution may involve implementing your own parallel communication interface using GPIO, Timers, and DMA (see AN4666 from ST as an example).
I’m sure there are many other possibilities as well, though, I’m not sure if any of them would be much less intricate/convoluted.
To expand on Matt’s points, even though it may be technically possible, I assume your goal is to speed up the acquisition process to take advantage of the LT2344-16’s speed. Chances are highly likely that anything you did to accomplish the parallel reading of the four data lines with an MCU would end up being no faster than you could read all of the data from a single SDO line, due to the overhead likely required to deal with the parallel data streams. To reiterate, high speed ADC’s are much better suited for interfacing with programmable logic devices (FPGAs or CPLDs), which are inherently parallel devices.
