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After enabling the MAC in the MSS by the system builder (in Libero) the next step after synthesizing, would be to manage the constraints. In this step I assigned the different Ports to their adequate Pin numbers based on the schematic of the VSC8541XMV (I chose GMII as interface)
Question: is it ok to leave it unassigned? or is there something that I am missing?
Part 2:
In order to use the Ethernet properly, the MAC should communicate with the PHY. As far as I understood, in order to make that using the MKR-Kit is through the configuration of the interface to use (GMII or MII or TBI) using Libero and the selected interface will be programmed in the fabric of the SoC FPGA.
Question: is that the only way?
What is the difference between using GMII or MII or TBI?
I still can’t find a tutorial or a full example about configurating and programming the Smatfuison2 to use Ethernet communication properly.
I believe the reason you can’t use pin 47 is because it is being reserved for probes. If you uncheck that box in the constraint manager, you should be able to continue. Unchecking the “Reserve Pins for Device Migration” isn’t necessary for this case, but will make sure you have all the pins available to you in the future.
Also it is expected that you use GMII with this board which allows up to 1 Gb/s speeds and uses a wider data bus than MII. TBI is a different interface altogether.
You may also want to enable the Management Interface for the MAC which it looks like they’re using. One thing to note is that you’ll have to convert the MDO and MDI signals to a bidirectional signal using the BIBUF block. (See the I2C pins in the Getting Started Guide for an example.)
The reason for the conversion is that the PHY uses a single bidirectional MDIO pin, but if you enable the management interface in Libero it gives you separate input and output signals, MDO and MDI, plus an output enable pin.
These are for the PHY’s Serial Management Interface (Section 3.10 in the data sheet). If I understood the data sheet correctly, managed/unmanaged modes only determine which settings are configurable via hardware pins.
I’m not deeply familiar with this PHY so you may end up not needing the management interface at all. I’m just assuming so based on the board’s schematic.
I have a logic design which includes a Core10100 IP core. IP core providesMII interface. Board has a VSC8541 that can support both MII and GMII but only GMII pins are given.
Is there a way to use MII interface with this PHY chip.
