If you are having the opposite problem of why won’t my FET turn on, where your n-channel FET is either not turning OFF or taking far too long to turn OFF, then it’s likely that you haven’t provided a low enough resistance path to GND for your FET gate.
As an example, consider the following simple circuit with a low-side n-channel FET used to turn on a 5V DC motor when the button (S1) is pressed.
The motor will run when the button is pressed, the problem is that it most likely won’t stop running when the button is unpressed (or it will run down very slowly). So why is this?
Well, first it’s useful to visualize that there is essentially an invisible (it’s unavoidable inside of a FET due to physics) capacitor connected between the gate and source terminals. In simple terms, you can think of switching the FET between ON/OFF states as filling/unfilling this capacitor with charge. Now, when the button is pressed and the switch (S1) closes, a quick burst of current will fill this capacitor and turn the FET ON, but when the button is unpressed and the switch (S1) opens where does the current in this capacitor have to go? There is also apt to be a very large Ohm parasitic resistance that will slowly discharge this capacitor, but depending on how large this could take a long time even in human observation terms (and an eternity in electronics time). So how do you fix it? Simply add a pull-down resistor of your own to speed up that invisible capacitor’s discharge.
Another important consideration is if you are driving the FET gate from another source such as a GPIO pin on a microcontroller. Some sources might act like the button switch above, where they can source (to charge) but not sink (to discharge) the current that feeds the capacitor’s invisible FET. Even if it can do both, you may run in to the same problem if the power rail of the source is turned off/disconnected suddenly (removing it’s ability to sink current), assuming the motor is being run from a different source that isn’t disconnected. It’s generally considered good design practice to always include pull-down resistors on the gates of FETs unless there is an explicit reason not to.