ADC & Clock Interfacing Help

Hello Everyone,

I am new to PCB development and I was hoping you great people could help me explain how to interface my ADC ( and my crystal (NX3225SA), and explain theory along the way. Some industry rule of thumbs would be great as well.

Here is what I know, the loaded capacitance (don’t know why a crystal needs to be capacitively loaded) is 8pF, assuming 5pF stray capacitance, then the paralled cap’s equal 3pF. Using the 2X rule of thumb this would give 6pF caps. Does this sound reasonable? If it doesn’t, why?

Looking at a snapshot of my schematic ( would these caps be placed on both I/O pins tied to ground?

Hopefully I have provided enough information.


A crystal can’t quite function on its own (they aren’t really “plug and play” per say). A voltage applied to a crystal will certainly provide energy for “oscillating”, however, the output will be really unstable as crystals are unpredictable without capacitance. I don’t know the full theory, but I do know that capacitors are often required to reduce noise on the output of said crystal and make the signal consistent. Could you provide a full part number for the crystal? The number provided (NX3225SA) is partial and many crystals are found in reference to that. If you don’t know the full number, what frequency is the crystal set at, Equivalent Series Resistance rating, and frequency stability in ppm?

The parallel cap can just be placed on the output portion (the left side from I/O to GND), doesn’t need to be on both. The input voltage will not oscillate at all. My question is why is there such a large resistor in series for the input voltage? This will cause a large voltage drop to occur if it is set at 1 MegOhm.

As for the term load-capacitance, this refers to the measured capacitance across the crystal terminals (pads). This is an important measurement in oscillation applications as this capacitance can cause major problems for leakage between terminals and cause more noise.

@Mr_Vancouver I’d respectfully call a time-out here; your text and your schematic snippet makes it appear to me as if you’re intending to simply hook a 20 MHz crystal up to the SCLK input of an ADS7952. If that indeed was your intent, it suggests a fundamental misunderstanding of the character of the ADC’s serial interface.

Any crystal or other frequency source in your system would not normally connect to an ADS7952 directly, but rather to the microcontroller, FPGA, or similar “intelligent” device having a serial interface peripheral which subsequently drives the SCLK pin in coordination with the SDI, SDO, and CS pins in order to transfer data and do something with it.

Questions of load capacitance and whatnot are all very pertinent and briefly discussed here, but are at best a topic of secondary importance to the issue of getting the lines drawn correctly in the block diagram of one’s system.

Hello Kaleb,

thank you for the thoughtful response, here is the link to the crystal’s spec’s:

The 1 Megaohm is because the drive level is 10micro-watts, so at 3.3V and that resistor I will get 10micro watts


with hindsight being 20/20 I actually knew this but for some reason did not connect the dot at this point, so thank you for respectively pointing this out and that article!