I’m doing a BGA design, and it’s almost impossible to do without vias on the pads. This generally means conductive filled vias, but I don’t see any info on that. Is this doable?
Also, I don’t see any option for annular width around a via. I found some talk about it in the forum, but no clear answers. Again, with a BGA, it’s very hard if the annular width is more than .1mm. It would be nice if the minimum annular width was specified, since that’s a pretty important detail.
Hello @corey,
Welcome to the DigiKey TechForum.
May I refer you to Petr Dvořák. I find his work fascinating, and he is very generous with his time.
Does the datasheet for your BGA present a recommended layout that you could follow?
Does the OEM for your BGA provide a demonstration board that you could reverse engineer?
Sincerely,
Aaron
Well, that’s not really helpful. I know how to do all this already. I actually need answers to my questions.
I have a 225 pin BGA. Routing all the pins I need out of it without vias on pads is pretty much impossible. And annular rings bigger than .1mm are also very hard. I could fudge a little, but not much.
Again:
Can you do vias on pads with DKRed or the PCB Builder? If so, how do I specify that the vias be filled?
What is the minimum annular ring size?
TIA,
-corey
Thank you for your inquiry.
You can probably do vias on pads, but you can’t specify the vias be filled for DKRed service.
We have the minimum annular ring size question come up in the past and the answer was 18mils (0.46mm).
EDIT: I’m looking at a board right now and yeah, they let me put vias in the middle of copper planes and pads. It’s looking like that’s a go.
The only remaining solution is to dogbone on the surface and drop to an inner layer.
Assuming 0.8 mm pitch for the BGA coupled with a 0.41 mm min via diameter doesn’t leave much room. But it may work.
A better question is will it work with a 4-layer board when we consider all the competing requirements.
It sounds like @corey has a fun project.
Cordially,
Aaron
Yeah, dogboning might work, but it doesn’t dissipate heat as well, I don’t think, which is another concern. I may have to do that, though. All those vias make routing the power, which is mostly on the inside pins, a whole lot harder. I have to route a 3 amps at 1.2V, then 1.8v, then 3.3V at 1 amp, so I can’t use standard thin traces. Then there’s all the decoupling capacitors. It’s messy.
There is a reference board, but it’s a 10 layer board. It is using dogboning. It’s using a 285 pin version of the chip with .65mm pitch on the BGA pins, so that’s right out. No way I could make that with .127mm traces and spacing.
Look on the bright side, @corey, when you figure this out you can always get a job designing FPGA PCB. There aren’t many people out there with that skill.
Yes, the center is dedicated to power as you stated. This may be an advantage especially if many adjacent pins share a common function e.g., 10 adjacent ground pins. No need to dogbone! Instead, use a surface plate to connect all pins and then drill (via) down with multiple vias. This may have thermal problems; however, the structure is common with other ICs that have a large central pad to dissipate power.
Thank you for the challenge as I learned a few things today.
Happy soldering,
Aaron
