Color Sensor Pmod Controller (VHDL)

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Color Sensor Pmod Controller (top level file): pmod_color_sensor.vhd (17.4 KB)

I2C Master (must be included in project): i2c_master.vhd (14.1 KB)


  • VHDL source code of a streamlined interface to Digilent’s PmodCOLOR (Pmod for AMS’s TCS3472 Color Light-to-Digital Converter)
  • Continually outputs latest light and color data on 4 parallel interfaces
  • Handles I2C communication and all data retrieval from the Color Sensor Pmod
  • Handles configuration of the color light-to-digital converter’s gain and atime parameters
  • User definable gain and atime
  • Configurable system clock rate


This details a VHDL component that handles interfacing an FPGA to Digilent’s Color Sensor Pmod, shown in Figure 1. Figure 2 illustrates a typical example of this Color Sensor Pmod Controller integrated into a system. As shown, the Color Sensor Pmod Controller connects to the Pmod ports and executes transactions to configure the Pmod and gather data. The data is continually updated and presented on 4 simple parallel interfaces, corresponding to the clear, red, green, and blue data values.

Figure 1. Digilent Color Sensor Pmod

Figure 2. Example Implementation

Theory of Operation

The Color Sensor Pmod Controller consists primarily of a state machine and an I2C Master component.

State Machine

The design uses the state machine depicted in Figure 3 to implement its operation. Upon start-up the component immediately enters the start state. It remains in this state for 100ms to ensure the Pmod has ample time to power-up. It then proceeds to the set_gain state, where it configures the gain of the ADCs within the TCS3472 color light-to-digital converter. Once complete, it enters the set_atime state to configure the integration time of these ADCs. It finishes the initialization sequence in the set_pon_aen state. Here, it sets the Power ON bit (PON) to activate the internal oscillator and also sets the ADC Enable bit (AEN) to activate the ADCs. The pause state implements a 2.4ms pause to give the Pmod time to gather data and update the data registers. In the following read_data state, the controller gathers the most recent light and color data from the Pmod. Finally, it outputs the data in the output_result state. It then continuously cycles between the pause, read_data, and output_result states to keep the light and color data updated. Although not shown in the state diagram, resetting the component at any time returns it to the start state.

Figure 3. State Diagram

I2C Master

During the set_gain, set_atime, set_pon_aen, and read_data states, the state machine controls an I2C Master component to communicate with the TCS3472 color light-to-digital converter on the Pmod. Documentation for the I2C Master is available here.

Configuring the Color Sensor Pmod Controller

The Color Sensor Pmod Controller is configured by setting the generic parameters in the entity.

System Clock Frequency

The generic parameter sys_clk_freq must be set to the frequency of the system clock provided to the Color Sensor Pmod Controller on its clk port.


The generic parameter gain sets the analog gain of the four ADCs that read the photodiodes in the TCS3472 color light-to-digital converter. This value can be adjusted to improve the accuracy of the color and light measurements for various lighting conditions. Valid gain values are 1, 4, 16, and 60. If any other value is assigned, the color sensor is configured with a default gain value of 1.

Integration Time

The generic parameter atime sets the integration time of the four ADCs that read the photodiodes in the TCS3472 color light-to-digital converter. The integration time affects both the resolution and sensitivity of the reading and can range from 2.4ms to 614ms. The parameter atime is a 2’s compliment value and is calculated from the desired integration time as shown in Equation 1.


For more details, see the top of page 15 in the TCS3472 datasheet (4.6 MB).

Port Descriptions

Table 1 describes the Color Sensor Pmod Controller’s ports.

Table 1. Port Descriptions


This Pmod has a 6-pin connector. Table 2 provides the pinout for this connector. The Color Sensor Pmod Controller’s ports need to be assigned to the FPGA pins that are routed to this connector as listed.

Table 2. Color Sensor Pmod Pinout and Connections to Color Sensor Pmod Controller

The Pmod also has several jumpers. JP1 and JP2 must be enabled (i.e. connected) to connect the required I2C pull-up resisters for SCL and SDA. JP3 and JP4 do not affect the Color Sensor Pmod Controller’s operation.


The reset_n input port must have a logic high for the Color Sensor Pmod Controller component to operate. A low logic level on this port asynchronously resets the component. During reset, the component aborts the current transaction with the Pmod and clears the clear, red, green, and blue data outputs and the i2c_ack_err output. Once released from reset, the Color Sensor Pmod Controller restarts its operation. It reconfigures the Pmod and resumes collecting and outputting light and color data.


This Color Sensor Pmod Controller is a programmable logic component that interfaces to Digilent’s PmodCOLOR (Color Sensor Pmod). It handles all communication with this Pmod to configure the Pmod’s color light-to-digital converter and provide a continual stream of updated light and color data on parallel outputs.

Related Topics

I2C Master (VHDL)


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