This article is practically one-to-one with “Getting started with the DE0-Nano-Soc”.
Same patch “0001-de0_nano0fixes.patch” is applied to the u-boot sources, same “socfpga_de0_nano_soc_defconfig” is used to configure the u-boot.
Is it a mistake, or exactly the same final build would work for both DE10-Nano and DE0-Nano-SoC kits?
Hi @Vlad correct, at the time i originally messed with this board, u-boot did have two different targets, however for some reason the target tied to this board actually failed to boot… While the other defconfig worked fine. I bet today, that issue is resolved, and the proper defconfig would be needed on a much newer branch…
It appears the instructions are also working with DE1-SoC board. The device tree include files in u-boot sources has a dedicated file for de1-soc, but it looks like it’s as empty as de10-nano include file when comparing to de0-nano-soc. So I’ve followed the same procedure, and the resulting image is working ok, at least it looks that way.
The defconfig file associated with the board has MTD device defined, but the board has no HPS-side qspi flash populated on the board, so I’d guess it would not work have I selected specifically de1-soc defconfig.
But this “success” also raises the question - isn’t ARM HPS will be overclocked on de10-nano or de1-soc? Since the PLL settings for CPU will be taken from de0-nano-soc handoff files (board/terasic/de0-nano-soc/qts), and the smaller Cyclone V chip on de0-nano-soc is rated for higher ARM CPU frequency (925MHz) as opposed to de10-nano and de1-soc (800MHz)
I’ve played a bit, the newer u-boot didn’t find the ethernet, I guess it should be related to the names of dts files and whatnot. The u-boot-socfpga from altera-opensource didn’t even start booting, no talking over the uart, and the user led was blinking dimly.
I’ve returned to the u-boot 2019 from the article, and replaced the board/de0-nano-soc/qts/ files with the ones from the de1-soc directory. That did the trick, the frequency reported by bdinfo command in u-boot console was shown as 800MHz.
But later in Intel docs I found that -C6 grade chips (DE1-SoC has -C6, at least on my revision) can run at 925MHz, so I’ve returned pll_cofig.h from de0-nano-soc. It’s odd that both Terasic manuals and the maintainers used 800MHz, while Intel say -C6 runs at 925MHz. Maybe related to the datasheets revisions, stating different values earlier.