Hot-Swap Controllers - Under-Voltage Lockout (UVLO) Principle

Semiconductor Integrated Circuits (ICs)
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Under-Voltage Lockout (UVLO) is critical for the power health of the LTC4210-3. Its core objectives are:

  • Preventing the controller from misoperating at low supply voltages, which avoids insufficient MOSFET drive, current limit failure, and system logic errors.
  • Ensuring the controller only enters an operational state when the supply voltage is sufficiently stable and reliable, protecting the power devices and load safety.

We use the ADI LTC4210 as an example to demonstrate a typical single-channel 5V hot-swappable connector.

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From the internal block diagram, the UVLO module is directly connected to the VCC pin (Pin 6) and go with the logic module:

1. Voltage Detection and Hysteresis Characteristics

  • Detection Target: Real-time monitoring of the VCC pin supply voltage (VCC = VIN = 5V in this circuit).
  • Threshold Definition:
    • Rising Threshold (VUVLO_R): Typical value 2.5V (when VCC is rising). UVLO is released when VCC ≥ 2.5V, and the chip prepares for operation.
    • Falling Threshold (VUVLO_F): Typical value 2.4V (when VCC is falling). UVLO is triggered when VCC ≤ 2.4V, resetting the chip.
    • Hysteresis Voltage: Approximately 100mV. This prevents frequent resets due to VCC fluctuations near the threshold, improving noise immunity.

2. Fault Response and State Control

  • VCC < 2.4V (Undervoltage State):
    • UVLO sends a reset signal to the logic module, placing the chip in reset mode.
    • The GATE pin is forced low, completely turning off the external MOSFET (Q1) and cutting off load power.
    • The TIMER capacitor discharges, resetting all timing/protection logic.
    • Soft-start cannot be initiated even if the ON pin meets the conditions.
  • VCC ≥ 2.5V (Normal State):
    • UVLO releases the reset, and the chip resumes operation.
    • The initial timing period and soft-start are only initiated if the ON pin level ≥ 1.3V.

3. Glitch Filter

The post-stage of the UVLO module includes a glitch filter (typically 30μs):

  • If VCC briefly drops below 2.4V but for < 30μs, UVLO will not trigger a reset.
  • Only when the undervoltage state persists for > 30μs is a true fault 判定，and shutdown is executed. This effectively filters out transient glitch interference on the power bus.

Combined with the Actual Scenario of the Application Circuit

In the 5V hot-swappable circuit you provided:

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  1. Power-Up Phase: VIN rises from 0 to 5V. The controller starts initial timing only after VCC crosses 2.5V and the ON pin is pulled high. This prevents the MOSFET from half-conducting and overheating at low voltage.
  2. Power Fluctuation Scenario: If the backplane power briefly drops to 2.3V for 20μs, the UVLO filter ignores this transient, and the system continues operating. If the drop persists for 40μs, UVLO triggers shutdown to protect the load.
  3. Power-Down Scenario: When VIN falls, UVLO immediately shuts down the MOSFET when VCC drops to 2.4V, preventing abnormal operation of the load at low voltage.

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